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ar71xx: enable MIB counters in the built-in switch of the AR934x

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SVN-Revision: 31476
This commit is contained in:
Gabor Juhos
2012-04-25 13:02:11 +00:00
parent cad1fa359d
commit a447f1810c
1 changed files with 11 additions and 2 deletions
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11
target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
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@@ -83,6 +83,7 @@
#define AR7240_MIB_AT_HALF_EN BIT(16) #define AR7240_MIB_AT_HALF_EN BIT(16)
#define AR7240_MIB_BUSY BIT(17) #define AR7240_MIB_BUSY BIT(17)
#define AR7240_MIB_FUNC_S 24 #define AR7240_MIB_FUNC_S 24
#define AR7240_MIB_FUNC_M BITM(3)
#define AR7240_MIB_FUNC_NO_OP 0x0 #define AR7240_MIB_FUNC_NO_OP 0x0
#define AR7240_MIB_FUNC_FLUSH 0x1 #define AR7240_MIB_FUNC_FLUSH 0x1
#define AR7240_MIB_FUNC_CAPTURE 0x3 #define AR7240_MIB_FUNC_CAPTURE 0x3
@@ -218,6 +219,8 @@
#define AR934X_AT_CTRL_AGE_EN BIT(17) #define AR934X_AT_CTRL_AGE_EN BIT(17)
#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18) #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
#define AR934X_MIB_ENABLE BIT(30)
#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
@@ -517,7 +520,8 @@ static int ar7240sw_capture_stats(struct ar7240sw *as)
write_lock(&as->stats_lock); write_lock(&as->stats_lock);
/* Capture the hardware statistics for all ports */ /* Capture the hardware statistics for all ports */
ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0, ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
(AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
(AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
/* Wait for the capturing to complete. */ /* Wait for the capturing to complete. */
@@ -579,6 +583,11 @@ static void ar7240sw_setup(struct ar7240sw *as)
/* Enable Broadcast frames transmitted to the CPU */ /* Enable Broadcast frames transmitted to the CPU */
ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK, ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
AR934X_FLOOD_MASK_BC_DP(0)); AR934X_FLOOD_MASK_BC_DP(0));
/* Enable MIB counters */
ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
AR934X_MIB_ENABLE);
} else { } else {
/* Enable ARP frame acknowledge, aging, MAC replacing */ /* Enable ARP frame acknowledge, aging, MAC replacing */
ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,