@@ -52,8 +52,14 @@
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#define MPMC_REG_SC3 0x0260
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/* Control register bits */
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#define MPMC_CTRL_AM ( 1 << 1 )
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#define MPMC_CTRL_DWB ( 1 << 3 )
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#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
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#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
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#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
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/* Status register bits */
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#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
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#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
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#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
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/* Dynamic Control register bits */
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#define MPMC_DC_CE ( 1 << 0 )
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