octeon: remove 3.18 support
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be> SVN-Revision: 47474
This commit is contained in:
Felix Fietkau
@@ -1,250 +0,0 @@
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CONFIG_64BIT=y
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CONFIG_64BIT_PHYS_ADDR=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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# CONFIG_ARCH_HAS_SG_CHAIN is not set
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
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CONFIG_BINFMT_ELF32=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLOCK_COMPAT=y
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# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
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CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
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CONFIG_BUILTIN_DTB=y
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# CONFIG_CAVIUM_CN63XXP1 is not set
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# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
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CONFIG_CAVIUM_OCTEON_LOCK_L2=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
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CONFIG_CAVIUM_OCTEON_SOC=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMPAT=y
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CONFIG_COMPAT_BRK=y
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CONFIG_COMPAT_NETLINK_MESSAGES=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_CAVIUM_OCTEON=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_HUGEPAGES=y
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CONFIG_CRAMFS=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_SPINLOCK=y
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CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DEVKMEM=y
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CONFIG_DMA_COHERENT=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_ENABLE_MUST_CHECK=y
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CONFIG_EXT4_FS=y
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CONFIG_FAT_FS=y
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CONFIG_FRAME_WARN=2048
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CONFIG_FS_MBCACHE=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_OCTEON=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_BPF_JIT=y
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CONFIG_HAVE_CC_STACKPROTECTOR=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_MEMORY_PRESENT=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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# CONFIG_HIGH_RES_TIMERS is not set
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CONFIG_HOLES_IN_ZONE=y
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# CONFIG_HUGETLBFS is not set
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_OCTEON=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IOMMU_HELPER=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD2=y
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CONFIG_KALLSYMS=y
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CONFIG_KEXEC=y
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CONFIG_LIBFDT=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MDIO_OCTEON=y
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CONFIG_MIPS=y
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CONFIG_MIPS32_COMPAT=y
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CONFIG_MIPS32_N32=y
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CONFIG_MIPS32_O32=y
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=7
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CONFIG_MIPS_L1_CACHE_SHIFT_7=y
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# CONFIG_MIPS_MACHINE is not set
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CONFIG_MIPS_PGD_C0_CONTEXT=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_OCTEON=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MODULES_USE_ELF_RELA=y
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CONFIG_MTD_BLOCK2MTD=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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# CONFIG_MTD_COMPLEX_MAPPINGS is not set
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CONFIG_MTD_PHYSMAP=y
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CONFIG_NEED_SG_DMA_LENGTH=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NLS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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# CONFIG_NO_IOPORT_MAP is not set
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CONFIG_NR_CPUS=16
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CONFIG_NR_CPUS_DEFAULT_16=y
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CONFIG_OCTEON_ETHERNET=y
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# CONFIG_OCTEON_ILM is not set
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CONFIG_OCTEON_MGMT_ETHERNET=y
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CONFIG_OCTEON_USB=y
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CONFIG_OCTEON_WDT=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS_PCI=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_MTD=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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# CONFIG_PARTITION_ADVANCED is not set
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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CONFIG_PHYS_ADDR_T_64BIT=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_POSIX_MQUEUE_SYSCTL=y
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# CONFIG_PREEMPT_RCU is not set
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CONFIG_PROC_PAGE_MONITOR=y
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RELAY=y
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CONFIG_RFS_ACCEL=y
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CONFIG_RPS=y
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CONFIG_SCHED_DEBUG=y
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CONFIG_SCSI=y
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CONFIG_SECCOMP=y
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CONFIG_SECCOMP_FILTER=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_SMP=y
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CONFIG_SPARSEMEM=y
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CONFIG_SPARSEMEM_STATIC=y
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CONFIG_STOP_MACHINE=y
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SWIOTLB=y
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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CONFIG_SYSVIPC_COMPAT=y
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CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y
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CONFIG_SYS_HAS_DMA_OPS=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
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CONFIG_SYS_SUPPORTS_HUGETLBFS=y
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CONFIG_SYS_SUPPORTS_SMP=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TREE_RCU=y
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CONFIG_UNINLINE_SPIN_UNLOCK=y
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_EHCI_HCD=y
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# CONFIG_USB_EHCI_HCD_PLATFORM is not set
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CONFIG_USB_EHCI_PCI=y
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CONFIG_USB_OCTEON2_COMMON=y
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CONFIG_USB_OCTEON_EHCI=y
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CONFIG_USB_OCTEON_OHCI=y
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CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_OHCI_HCD=y
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# CONFIG_USB_OHCI_HCD_PLATFORM is not set
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CONFIG_USB_STORAGE=y
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CONFIG_USB_SUPPORT=y
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# CONFIG_USB_UHCI_HCD is not set
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CONFIG_USE_OF=y
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CONFIG_VFAT_FS=y
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||||||
CONFIG_VM_EVENT_COUNTERS=y
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||||||
CONFIG_WEAK_ORDERING=y
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||||||
CONFIG_XPS=y
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||||||
CONFIG_ZLIB_INFLATE=y
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CONFIG_ZONE_DMA32=y
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CONFIG_ZONE_DMA_FLAG=0
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@@ -1,31 +0,0 @@
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--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
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+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
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|
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@@ -228,6 +228,8 @@ enum cvmx_board_types_enum {
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|
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*/
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CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
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|
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CVMX_BOARD_TYPE_UBNT_E100 = 20002,
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+ CVMX_BOARD_TYPE_UBNT_E200 = 20003,
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+ CVMX_BOARD_TYPE_UBNT_E220 = 20005,
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CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
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CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
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@@ -328,6 +330,8 @@ static inline const char *cvmx_board_typ
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/* Customer private range */
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
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|
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+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)
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|
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+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)
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|
||||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
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|
||||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
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|
||||||
}
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|
||||||
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
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|
||||||
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
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|
||||||
@@ -195,6 +195,8 @@ int cvmx_helper_board_get_mii_address(in
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|
||||||
return 8;
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|
||||||
else
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|
||||||
return -1;
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|
||||||
+ case CVMX_BOARD_TYPE_UBNT_E200:
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|
||||||
+ return -1;
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|
||||||
}
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|
||||||
|
|
||||||
/* Some unknown board. Somebody forgot to update this function... */
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|
||||||
@@ -1,34 +0,0 @@
|
|||||||
--- a/drivers/staging/octeon/ethernet.c
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|
||||||
+++ b/drivers/staging/octeon/ethernet.c
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|
||||||
@@ -620,6 +620,7 @@ static int cvm_oct_probe(struct platform
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|
||||||
int interface;
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|
||||||
int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
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|
||||||
int qos;
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|
||||||
+ int i;
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|
||||||
struct device_node *pip;
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|
||||||
|
|
||||||
octeon_mdiobus_force_mod_depencency();
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|
||||||
@@ -705,13 +706,19 @@ static int cvm_oct_probe(struct platform
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|
||||||
}
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|
||||||
|
|
||||||
num_interfaces = cvmx_helper_get_number_of_interfaces();
|
|
||||||
- for (interface = 0; interface < num_interfaces; interface++) {
|
|
||||||
- cvmx_helper_interface_mode_t imode =
|
|
||||||
- cvmx_helper_interface_get_mode(interface);
|
|
||||||
- int num_ports = cvmx_helper_ports_on_interface(interface);
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|
||||||
+ for (i = 0; i < num_interfaces; i++) {
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|
||||||
+ cvmx_helper_interface_mode_t imode;
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|
||||||
+ int interface;
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|
||||||
+ int num_ports;
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|
||||||
int port;
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|
||||||
int port_index;
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|
||||||
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|
||||||
+ interface = i;
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|
||||||
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200)
|
|
||||||
+ interface = num_interfaces - (i + 1);
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|
||||||
+
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|
||||||
+ num_ports = cvmx_helper_ports_on_interface(interface);
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|
||||||
+ imode = cvmx_helper_interface_get_mode(interface);
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|
||||||
for (port_index = 0,
|
|
||||||
port = cvmx_helper_get_ipd_port(interface, 0);
|
|
||||||
port < cvmx_helper_get_ipd_port(interface, num_ports);
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
--- a/arch/mips/cavium-octeon/octeon-platform.c
|
|
||||||
+++ b/arch/mips/cavium-octeon/octeon-platform.c
|
|
||||||
@@ -82,7 +82,7 @@ static int __init octeon_ehci_device_ini
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Only Octeon2 has ehci/ohci */
|
|
||||||
- if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
|
|
||||||
+ if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
|
|
||||||
return 0;
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|
||||||
|
|
||||||
if (octeon_is_simulation() || usb_disabled())
|
|
||||||
@@ -131,7 +131,7 @@ static int __init octeon_ohci_device_ini
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Only Octeon2 has ehci/ohci */
|
|
||||||
- if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
|
|
||||||
+ if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
if (octeon_is_simulation() || usb_disabled())
|
|
||||||
@@ -1,21 +0,0 @@
|
|||||||
--- a/arch/mips/cavium-octeon/setup.c
|
|
||||||
+++ b/arch/mips/cavium-octeon/setup.c
|
|
||||||
@@ -50,6 +50,9 @@ extern void pci_console_init(const char
|
|
||||||
|
|
||||||
static unsigned long long MAX_MEMORY = 512ull << 20;
|
|
||||||
|
|
||||||
+DEFINE_SEMAPHORE(octeon_bootbus_sem);
|
|
||||||
+EXPORT_SYMBOL(octeon_bootbus_sem);
|
|
||||||
+
|
|
||||||
struct octeon_boot_descriptor *octeon_boot_desc_ptr;
|
|
||||||
|
|
||||||
struct cvmx_bootinfo *octeon_bootinfo;
|
|
||||||
--- a/arch/mips/include/asm/octeon/octeon.h
|
|
||||||
+++ b/arch/mips/include/asm/octeon/octeon.h
|
|
||||||
@@ -252,4 +252,6 @@ void octeon_irq_set_ip4_handler(octeon_i
|
|
||||||
|
|
||||||
extern void octeon_fixup_irqs(void);
|
|
||||||
|
|
||||||
+extern struct semaphore octeon_bootbus_sem;
|
|
||||||
+
|
|
||||||
#endif /* __ASM_OCTEON_OCTEON_H */
|
|
||||||
@@ -1,103 +0,0 @@
|
|||||||
--- a/arch/mips/include/asm/octeon/octeon-model.h
|
|
||||||
+++ b/arch/mips/include/asm/octeon/octeon-model.h
|
|
||||||
@@ -45,6 +45,7 @@
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OCTEON_FAMILY_MASK 0x00ffff00
|
|
||||||
+#define OCTEON_PRID_MASK 0x00ffffff
|
|
||||||
|
|
||||||
/* Flag bits in top byte */
|
|
||||||
/* Ignores revision in model checks */
|
|
||||||
@@ -63,6 +64,46 @@
|
|
||||||
#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
|
|
||||||
/* Match all cnf7XXX Octeon models. */
|
|
||||||
#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000
|
|
||||||
+/* Match all cn7XXX Octeon models. */
|
|
||||||
+#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000
|
|
||||||
+#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \
|
|
||||||
+ OM_MATCH_6XXX_FAMILY_MODELS | \
|
|
||||||
+ OM_MATCH_F7XXX_FAMILY_MODELS | \
|
|
||||||
+ OM_MATCH_7XXX_FAMILY_MODELS)
|
|
||||||
+/*
|
|
||||||
+ * CN7XXX models with new revision encoding
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN73XX_PASS1_0 0x000d9700
|
|
||||||
+#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
|
|
||||||
+#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
|
|
||||||
+ OM_IGNORE_MINOR_REVISION)
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN70XX_PASS1_0 0x000d9600
|
|
||||||
+#define OCTEON_CN70XX_PASS1_1 0x000d9601
|
|
||||||
+#define OCTEON_CN70XX_PASS1_2 0x000d9602
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN70XX_PASS2_0 0x000d9608
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
|
|
||||||
+#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \
|
|
||||||
+ OM_IGNORE_MINOR_REVISION)
|
|
||||||
+#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \
|
|
||||||
+ OM_IGNORE_MINOR_REVISION)
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN71XX OCTEON_CN70XX
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN78XX_PASS1_0 0x000d9500
|
|
||||||
+#define OCTEON_CN78XX_PASS1_1 0x000d9501
|
|
||||||
+#define OCTEON_CN78XX_PASS2_0 0x000d9508
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
|
|
||||||
+#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \
|
|
||||||
+ OM_IGNORE_MINOR_REVISION)
|
|
||||||
+#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \
|
|
||||||
+ OM_IGNORE_MINOR_REVISION)
|
|
||||||
+
|
|
||||||
+#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* CNF7XXX models with new revision encoding
|
|
||||||
@@ -217,6 +258,10 @@
|
|
||||||
#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
|
|
||||||
#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
|
|
||||||
#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
|
|
||||||
+#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \
|
|
||||||
+ OM_MATCH_F7XXX_FAMILY_MODELS)
|
|
||||||
+#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \
|
|
||||||
+ OM_MATCH_7XXX_FAMILY_MODELS)
|
|
||||||
|
|
||||||
/* These are used to cover entire families of OCTEON processors */
|
|
||||||
#define OCTEON_FAM_1 (OCTEON_CN3XXX)
|
|
||||||
@@ -288,9 +333,16 @@ static inline uint64_t cvmx_read_csr(uin
|
|
||||||
((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
|
|
||||||
&& __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
|
|
||||||
((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
|
|
||||||
- && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
|
|
||||||
((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
|
|
||||||
- && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
|
|
||||||
+ ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
|
|
||||||
+ ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
|
|
||||||
+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
|
|
||||||
((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
|
|
||||||
&& (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
|
|
||||||
)))
|
|
||||||
@@ -326,6 +378,15 @@ static inline int __octeon_is_model_runt
|
|
||||||
#define OCTEON_IS_COMMON_BINARY() 1
|
|
||||||
#undef OCTEON_MODEL
|
|
||||||
|
|
||||||
+#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX)
|
|
||||||
+#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX)
|
|
||||||
+#define OCTEON_IS_OCTEON2() \
|
|
||||||
+ (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
|
|
||||||
+
|
|
||||||
+#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX)
|
|
||||||
+
|
|
||||||
+#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
|
|
||||||
+
|
|
||||||
const char *octeon_model_get_string(uint32_t chip_id);
|
|
||||||
const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,47 +0,0 @@
|
|||||||
--- a/arch/mips/cavium-octeon/setup.c
|
|
||||||
+++ b/arch/mips/cavium-octeon/setup.c
|
|
||||||
@@ -609,6 +609,35 @@ void octeon_user_io_init(void)
|
|
||||||
write_c0_derraddr1(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
+#ifdef CONFIG_IMAGE_CMDLINE_HACK
|
|
||||||
+extern char __image_cmdline[];
|
|
||||||
+
|
|
||||||
+static int __init octeon_use_image_cmdline(void)
|
|
||||||
+{
|
|
||||||
+ char *p = __image_cmdline;
|
|
||||||
+ int replace = 0;
|
|
||||||
+
|
|
||||||
+ if (*p == '-') {
|
|
||||||
+ replace = 1;
|
|
||||||
+ p++;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ if (*p == '\0')
|
|
||||||
+ return 0;
|
|
||||||
+
|
|
||||||
+ if (replace) {
|
|
||||||
+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
|
|
||||||
+ } else {
|
|
||||||
+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
|
|
||||||
+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ return 1;
|
|
||||||
+}
|
|
||||||
+#else
|
|
||||||
+static inline int octeon_use_image_cmdline(void) { return 0; }
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
/**
|
|
||||||
* Early entry point for arch setup
|
|
||||||
*/
|
|
||||||
@@ -798,6 +827,8 @@ void __init prom_init(void)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
+ octeon_use_image_cmdline();
|
|
||||||
+
|
|
||||||
if (strstr(arcs_cmdline, "console=") == NULL) {
|
|
||||||
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
|
|
||||||
strcat(arcs_cmdline, " console=ttyS0,115200");
|
|
||||||
Reference in New Issue
Block a user