kernel: update kernel 4.4 to 4.4.61
Signed-off-by: Jo-Philipp Wich <jo@mein.io>
This commit is contained in:
		@@ -3,11 +3,11 @@
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LINUX_RELEASE?=1
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LINUX_VERSION-3.18 = .43
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LINUX_VERSION-4.4 = .59
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LINUX_VERSION-4.4 = .61
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LINUX_VERSION-4.9 = .20
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LINUX_KERNEL_HASH-3.18.43 = 1236e8123a6ce537d5029232560966feed054ae31776fe8481dd7d18cdd5492c
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LINUX_KERNEL_HASH-4.4.59 = 64e9523c4c7fdaf391a16dd19541bb58e39943cb2151aa0c3d15b6aeaba996ca
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LINUX_KERNEL_HASH-4.4.61 = 30dee7164615ad8184eba4ea6f4906b3ceb2fe462a8a4a929c8e9aab8d4a31da
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LINUX_KERNEL_HASH-4.9.20 = 48660806dd32fb8dcbcf5932291bf6cc7d29240070372230871e0f56fea81341
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ifdef KERNEL_PATCHVER
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@@ -416,7 +416,7 @@
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 	/*
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -943,6 +943,9 @@ build_get_pgde32(u32 **p, unsigned int t
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@@ -960,6 +960,9 @@ build_get_pgde32(u32 **p, unsigned int t
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 		uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
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 		uasm_i_addu(p, ptr, tmp, ptr);
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 #else
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@@ -426,7 +426,7 @@
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 		UASM_i_LA_mostly(p, ptr, pgdc);
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 #endif
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 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
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@@ -1284,6 +1287,9 @@ static void build_r4000_tlb_refill_handl
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@@ -1301,6 +1304,9 @@ static void build_r4000_tlb_refill_handl
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 #ifdef CONFIG_64BIT
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 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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 #else
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@@ -436,7 +436,7 @@
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 		build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
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 #endif
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@@ -1295,6 +1301,9 @@ static void build_r4000_tlb_refill_handl
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@@ -1312,6 +1318,9 @@ static void build_r4000_tlb_refill_handl
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 		build_update_entries(&p, K0, K1);
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 		build_tlb_write_entry(&p, &l, &r, tlb_random);
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 		uasm_l_leave(&l, p);
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@@ -446,7 +446,7 @@
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 		uasm_i_eret(&p); /* return from trap */
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 	}
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 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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@@ -1871,6 +1880,9 @@ build_r4000_tlbchange_handler_head(u32 *
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@@ -1888,6 +1897,9 @@ build_r4000_tlbchange_handler_head(u32 *
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 #ifdef CONFIG_64BIT
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 	build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
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 #else
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@@ -456,7 +456,7 @@
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 	build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
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 #endif
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@@ -1917,6 +1929,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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@@ -1934,6 +1946,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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 	build_tlb_write_entry(p, l, r, tlb_indexed);
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 	uasm_l_leave(l, *p);
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 	build_restore_work_registers(p);
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@@ -45,7 +45,7 @@
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 			/* disable */
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 			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
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 				LTQ_EIU_EXIN_INEN);
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@@ -343,10 +343,10 @@ static int icu_map(struct irq_domain *d,
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@@ -344,10 +344,10 @@ static int icu_map(struct irq_domain *d,
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 		return 0;
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 	for (i = 0; i < exin_avail; i++)
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@@ -58,7 +58,7 @@
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 	return 0;
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 }
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@@ -441,14 +441,14 @@ int __init icu_of_init(struct device_nod
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@@ -437,14 +437,14 @@ int __init icu_of_init(struct device_nod
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 	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
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 	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
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 		/* find out how many external irq sources we have */
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@@ -1,87 +0,0 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Thu, 19 Jan 2017 12:14:44 +0100
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Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
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With the IRQ stack changes integrated, the XRX200 devices started
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emitting a constant stream of kernel messages like this:
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[  565.415310] Spurious IRQ: CAUSE=0x1100c300
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This appears to be caused by IP0 firing for some reason without being
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handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
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calling do_IRQ for all MIPS CPU interrupts.
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Cc: john@phrozen.org
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Cc: stable@vger.kernel.org
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
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 DEFINE_HWx_IRQDISPATCH(5)
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 #endif
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+static void ltq_hw_irq_handler(struct irq_desc *desc)
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+{
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+	ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
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+}
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+
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 #ifdef CONFIG_MIPS_MT_SMP
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 void __init arch_init_ipiirq(int irq, struct irqaction *action)
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 {
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@@ -315,23 +320,19 @@ static struct irqaction irq_call = {
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 asmlinkage void plat_irq_dispatch(void)
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 {
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 	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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-	unsigned int i;
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+	int irq;
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-	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
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-		do_IRQ(MIPS_CPU_TIMER_IRQ);
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-		goto out;
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-	} else {
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-		for (i = 0; i < MAX_IM; i++) {
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-			if (pending & (CAUSEF_IP2 << i)) {
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-				ltq_hw_irqdispatch(i);
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-				goto out;
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-			}
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-		}
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+	if (!pending) {
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+		spurious_interrupt();
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+		return;
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 	}
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-	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
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-out:
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-	return;
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+	pending >>= CAUSEB_IP;
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+	while (pending) {
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+		irq = fls(pending) - 1;
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+		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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+		pending &= ~BIT(irq);
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+	}
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 }
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 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
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 	.map = icu_map,
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 };
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-static struct irqaction cascade = {
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-	.handler = no_action,
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-	.name = "cascade",
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-};
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-
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 int __init icu_of_init(struct device_node *node, struct device_node *parent)
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 {
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 	struct device_node *eiu_node;
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@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
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 	mips_cpu_irq_init();
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 	for (i = 0; i < MAX_IM; i++)
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-		setup_irq(i + 2, &cascade);
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+		irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
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 	if (cpu_has_vint) {
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 		pr_info("Setting up vectored interrupts\n");
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@@ -1,21 +0,0 @@
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From 2583143af8111d430bdca0268b6cdb7ccc7c3f9d Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Fri, 13 Jan 2017 05:40:04 +0100
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Subject: [PATCH] mips: ralink/rt3883: fix typo in pinctrl lna_g_func
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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 arch/mips/ralink/rt3883.c | 2 +-
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 1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/ralink/rt3883.c
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+++ b/arch/mips/ralink/rt3883.c
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@@ -36,7 +36,7 @@ static struct rt2880_pmx_func uartlite_f
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 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
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 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
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 static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
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-static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
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+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
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 static struct rt2880_pmx_func pci_func[] = {
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 	FUNC("pci-dev", 0, 40, 32),
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 	FUNC("pci-host2", 1, 40, 32),
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