Add basic 2.6.24 support for rb532, korina napi code has to be adapted to work
SVN-Revision: 11844
This commit is contained in:
Florian Fainelli
173
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/ddr.h
Normal file
173
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/ddr.h
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@@ -0,0 +1,173 @@
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#ifndef __IDT_DDR_H__
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#define __IDT_DDR_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* DDR register definition.
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*
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* File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Update :
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* $Log: ddr.h,v $
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* Revision 1.2 2002/06/06 18:34:03 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.1 2002/05/29 17:33:21 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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*
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******************************************************************************/
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enum
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{
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DDR0_PhysicalAddress = 0x18018000,
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DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
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DDR0_VirtualAddress = 0xb8018000,
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DDR_VirtualAddress = DDR0_VirtualAddress, // Default
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} ;
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typedef struct DDR_s
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{
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u32 ddrbase ;
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u32 ddrmask ;
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u32 res1;
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u32 res2;
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u32 ddrc ;
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u32 ddrabase ;
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u32 ddramask ;
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u32 ddramap ;
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u32 ddrcust;
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u32 ddrrdc;
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u32 ddrspare;
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} volatile *DDR_t ;
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enum
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{
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DDR0BASE_baseaddr_b = 16,
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DDR0BASE_baseaddr_m = 0xffff0000,
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DDR0MASK_mask_b = 16,
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DDR0MASK_mask_m = 0xffff0000,
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DDR1BASE_baseaddr_b = 16,
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DDR1BASE_baseaddr_m = 0xffff0000,
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DDR1MASK_mask_b = 16,
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DDR1MASK_mask_m = 0xffff0000,
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DDRC_ata_b = 5,
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DDRC_ata_m = 0x000000E0,
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DDRC_dbw_b = 8,
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DDRC_dbw_m = 0x00000100,
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DDRC_wr_b = 9,
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DDRC_wr_m = 0x00000600,
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DDRC_ps_b = 11,
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DDRC_ps_m = 0x00001800,
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DDRC_dtype_b = 13,
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DDRC_dtype_m = 0x0000e000,
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DDRC_rfc_b = 16,
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DDRC_rfc_m = 0x000f0000,
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DDRC_rp_b = 20,
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DDRC_rp_m = 0x00300000,
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DDRC_ap_b = 22,
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DDRC_ap_m = 0x00400000,
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DDRC_rcd_b = 23,
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DDRC_rcd_m = 0x01800000,
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DDRC_cl_b = 25,
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DDRC_cl_m = 0x06000000,
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DDRC_dbm_b = 27,
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DDRC_dbm_m = 0x08000000,
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DDRC_sds_b = 28,
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DDRC_sds_m = 0x10000000,
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DDRC_atp_b = 29,
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DDRC_atp_m = 0x60000000,
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DDRC_re_b = 31,
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DDRC_re_m = 0x80000000,
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DDRRDC_ces_b = 0,
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DDRRDC_ces_m = 0x00000001,
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DDRRDC_ace_b = 1,
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DDRRDC_ace_m = 0x00000002,
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DDRABASE_baseaddr_b = 16,
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DDRABASE_baseaddr_m = 0xffff0000,
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DDRAMASK_mask_b = 16,
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DDRAMASK_mask_m = 0xffff0000,
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DDRAMAP_map_b = 16,
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DDRAMAP_map_m = 0xffff0000,
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DDRCUST_cs_b = 0,
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DDRCUST_cs_m = 0x00000003,
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DDRCUST_we_b = 2,
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DDRCUST_we_m = 0x00000004,
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DDRCUST_ras_b = 3,
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DDRCUST_ras_m = 0x00000008,
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DDRCUST_cas_b = 4,
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DDRCUST_cas_m = 0x00000010,
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DDRCUST_cke_b = 5,
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DDRCUST_cke_m = 0x00000020,
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DDRCUST_ba_b = 6,
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DDRCUST_ba_m = 0x000000c0,
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RCOUNT_rcount_b = 0,
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RCOUNT_rcount_m = 0x0000ffff,
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RCOMPARE_rcompare_b = 0,
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RCOMPARE_rcompare_m = 0x0000ffff,
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RTC_ce_b = 0,
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RTC_ce_m = 0x00000001,
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RTC_to_b = 1,
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RTC_to_m = 0x00000002,
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RTC_rqe_b = 2,
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RTC_rqe_m = 0x00000004,
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DDRDQSC_dm_b = 0,
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DDRDQSC_dm_m = 0x00000003,
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DDRDQSC_dqsbs_b = 2,
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DDRDQSC_dqsbs_m = 0x000000fc,
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DDRDQSC_db_b = 8,
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DDRDQSC_db_m = 0x00000100,
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DDRDQSC_dbsp_b = 9,
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DDRDQSC_dbsp_m = 0x01fffe00,
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DDRDQSC_bdp_b = 25,
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DDRDQSC_bdp_m = 0x7e000000,
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DDRDLLC_eao_b = 0,
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DDRDLLC_eao_m = 0x00000001,
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DDRDLLC_eo_b = 1,
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DDRDLLC_eo_m = 0x0000003e,
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DDRDLLC_fs_b = 6,
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DDRDLLC_fs_m = 0x000000c0,
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DDRDLLC_as_b = 8,
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DDRDLLC_as_m = 0x00000700,
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DDRDLLC_sp_b = 11,
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DDRDLLC_sp_m = 0x001ff800,
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DDRDLLFC_men_b = 0,
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DDRDLLFC_men_m = 0x00000001,
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DDRDLLFC_aen_b = 1,
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DDRDLLFC_aen_m = 0x00000002,
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DDRDLLFC_ff_b = 2,
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DDRDLLFC_ff_m = 0x00000004,
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DDRDLLTA_addr_b = 2,
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DDRDLLTA_addr_m = 0xfffffffc,
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DDRDLLED_dbe_b = 0,
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DDRDLLED_dbe_m = 0x00000001,
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DDRDLLED_dte_b = 1,
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DDRDLLED_dte_m = 0x00000002,
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} ;
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#endif // __IDT_DDR_H__
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168
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/dma.h
Normal file
168
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/dma.h
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@@ -0,0 +1,168 @@
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#ifndef __IDT_DMA_H__
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#define __IDT_DMA_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* DMA register definition.
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*
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* File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Update :
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* $Log: dma.h,v $
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* Revision 1.3 2002/06/06 18:34:03 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.2 2002/06/05 18:30:46 astichte
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* Removed IDTField
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*
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* Revision 1.1 2002/05/29 17:33:21 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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*
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******************************************************************************/
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enum
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{
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DMA0_PhysicalAddress = 0x18040000,
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DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
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DMA0_VirtualAddress = 0xb8040000,
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DMA_VirtualAddress = DMA0_VirtualAddress, // Default
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} ;
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/*
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* DMA descriptor (in physical memory).
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*/
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typedef struct DMAD_s
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{
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u32 control ; // Control. use DMAD_*
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u32 ca ; // Current Address.
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u32 devcs ; // Device control and status.
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u32 link ; // Next descriptor in chain.
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} volatile *DMAD_t ;
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enum
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{
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DMAD_size = sizeof (struct DMAD_s),
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DMAD_count_b = 0, // in DMAD_t -> control
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DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
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DMAD_ds_b = 20, // in DMAD_t -> control
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DMAD_ds_m = 0x00300000, // in DMAD_t -> control
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DMAD_ds_ethRcv_v = 0,
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DMAD_ds_ethXmt_v = 0,
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DMAD_ds_memToFifo_v = 0,
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DMAD_ds_fifoToMem_v = 0,
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DMAD_ds_pciToMem_v = 0,
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DMAD_ds_memToPci_v = 0,
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DMAD_devcmd_b = 22, // in DMAD_t -> control
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DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
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DMAD_devcmd_byte_v = 0, //memory-to-memory
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DMAD_devcmd_halfword_v = 1, //memory-to-memory
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DMAD_devcmd_word_v = 2, //memory-to-memory
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DMAD_devcmd_2words_v = 3, //memory-to-memory
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DMAD_devcmd_4words_v = 4, //memory-to-memory
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DMAD_devcmd_6words_v = 5, //memory-to-memory
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DMAD_devcmd_8words_v = 6, //memory-to-memory
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DMAD_devcmd_16words_v = 7, //memory-to-memory
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DMAD_cof_b = 25, // chain on finished
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DMAD_cof_m = 0x02000000, //
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DMAD_cod_b = 26, // chain on done
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DMAD_cod_m = 0x04000000, //
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DMAD_iof_b = 27, // interrupt on finished
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DMAD_iof_m = 0x08000000, //
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DMAD_iod_b = 28, // interrupt on done
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DMAD_iod_m = 0x10000000, //
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DMAD_t_b = 29, // terminated
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DMAD_t_m = 0x20000000, //
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DMAD_d_b = 30, // done
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DMAD_d_m = 0x40000000, //
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DMAD_f_b = 31, // finished
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DMAD_f_m = 0x80000000, //
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} ;
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/*
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* DMA register (within Internal Register Map).
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*/
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struct DMA_Chan_s
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{
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u32 dmac ; // Control.
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u32 dmas ; // Status.
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u32 dmasm ; // Mask.
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u32 dmadptr ; // Descriptor pointer.
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u32 dmandptr ; // Next descriptor pointer.
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};
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typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
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//DMA_Channels use DMACH_count instead
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enum
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{
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DMAC_run_b = 0, //
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DMAC_run_m = 0x00000001, //
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DMAC_dm_b = 1, // done mask
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DMAC_dm_m = 0x00000002, //
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DMAC_mode_b = 2, //
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DMAC_mode_m = 0x0000000c, //
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DMAC_mode_auto_v = 0,
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DMAC_mode_burst_v = 1,
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DMAC_mode_transfer_v = 2, //usually used
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DMAC_mode_reserved_v = 3,
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DMAC_a_b = 4, //
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DMAC_a_m = 0x00000010, //
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DMAS_f_b = 0, // finished (sticky)
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DMAS_f_m = 0x00000001, //
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DMAS_d_b = 1, // done (sticky)
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DMAS_d_m = 0x00000002, //
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DMAS_c_b = 2, // chain (sticky)
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DMAS_c_m = 0x00000004, //
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DMAS_e_b = 3, // error (sticky)
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DMAS_e_m = 0x00000008, //
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DMAS_h_b = 4, // halt (sticky)
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DMAS_h_m = 0x00000010, //
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DMASM_f_b = 0, // finished (1=mask)
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DMASM_f_m = 0x00000001, //
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DMASM_d_b = 1, // done (1=mask)
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DMASM_d_m = 0x00000002, //
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DMASM_c_b = 2, // chain (1=mask)
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DMASM_c_m = 0x00000004, //
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DMASM_e_b = 3, // error (1=mask)
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DMASM_e_m = 0x00000008, //
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DMASM_h_b = 4, // halt (1=mask)
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DMASM_h_m = 0x00000010, //
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} ;
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/*
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* DMA channel definitions
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*/
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enum
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{
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DMACH_ethRcv = 0,
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DMACH_ethXmt = 1,
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DMACH_memToFifo = 2,
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DMACH_fifoToMem = 3,
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DMACH_pciToMem = 4,
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DMACH_memToPci = 5,
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DMACH_count //must be last
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};
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typedef struct DMAC_s
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{
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struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
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} volatile *DMA_t ;
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#endif // __IDT_DMA_H__
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@@ -0,0 +1,72 @@
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#ifndef __IDT_DMA_V_H__
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#define __IDT_DMA_V_H__
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/*******************************************************************************
|
||||
*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* DMA register definition.
|
||||
*
|
||||
* File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
|
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*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
* Update :
|
||||
* $Log: dma.h,v $
|
||||
* Revision 1.3 2002/06/06 18:34:03 astichte
|
||||
* Added XXX_PhysicalAddress and XXX_VirtualAddress
|
||||
*
|
||||
* Revision 1.2 2002/06/05 18:30:46 astichte
|
||||
* Removed IDTField
|
||||
*
|
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* Revision 1.1 2002/05/29 17:33:21 sysarch
|
||||
* jba File moved from vcode/include/idt/acacia
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||||
*
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*
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******************************************************************************/
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#include <asm/rc32434/dma.h>
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#include <asm/rc32434/rc32434.h>
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#define DMA_CHAN_OFFSET 0x14
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#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
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#define DMA_COUNT(count) \
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((count) & DMAD_count_m)
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#define DMA_HALT_TIMEOUT 500
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||||
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||||
static inline int rc32434_halt_dma(DMA_Chan_t ch)
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||||
{
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int timeout=1;
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if (local_readl(&ch->dmac) & DMAC_run_m) {
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||||
local_writel(0, &ch->dmac);
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for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
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if (local_readl(&ch->dmas) & DMAS_h_m) {
|
||||
local_writel(0, &ch->dmas);
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break;
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||||
}
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||||
}
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||||
}
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||||
|
||||
return timeout ? 0 : 1;
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}
|
||||
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static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
|
||||
{
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||||
local_writel(0, &ch->dmandptr);
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local_writel(dma_addr, &ch->dmadptr);
|
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}
|
||||
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||||
static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
|
||||
{
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local_writel(dma_addr, &ch->dmandptr);
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}
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||||
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#endif // __IDT_DMA_V_H__
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||||
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||||
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||||
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||||
|
||||
|
||||
|
||||
|
||||
320
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/eth.h
Normal file
320
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/eth.h
Normal file
@@ -0,0 +1,320 @@
|
||||
#ifndef __IDT_ETH_H__
|
||||
#define __IDT_ETH_H__
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Ethernet register definition.
|
||||
*
|
||||
* File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
|
||||
*
|
||||
* Author : Allen.Stichter@idt.com
|
||||
* Date : 20020605
|
||||
* Update :
|
||||
* $Log: eth.h,v $
|
||||
* Revision 1.3 2002/06/06 18:34:04 astichte
|
||||
* Added XXX_PhysicalAddress and XXX_VirtualAddress
|
||||
*
|
||||
* Revision 1.2 2002/06/05 18:19:46 astichte
|
||||
* Added
|
||||
*
|
||||
* Revision 1.1 2002/05/29 17:33:22 sysarch
|
||||
* jba File moved from vcode/include/idt/acacia
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
enum
|
||||
{
|
||||
ETH0_PhysicalAddress = 0x18060000,
|
||||
ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
|
||||
|
||||
ETH0_VirtualAddress = 0xb8060000,
|
||||
ETH_VirtualAddress = ETH0_VirtualAddress, // Default
|
||||
} ;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 ethintfc ;
|
||||
u32 ethfifott ;
|
||||
u32 etharc ;
|
||||
u32 ethhash0 ;
|
||||
u32 ethhash1 ;
|
||||
u32 ethu0 [4] ; // Reserved.
|
||||
u32 ethpfs ;
|
||||
u32 ethmcp ;
|
||||
u32 eth_u1 [10] ; // Reserved.
|
||||
u32 ethspare ;
|
||||
u32 eth_u2 [42] ; // Reserved.
|
||||
u32 ethsal0 ;
|
||||
u32 ethsah0 ;
|
||||
u32 ethsal1 ;
|
||||
u32 ethsah1 ;
|
||||
u32 ethsal2 ;
|
||||
u32 ethsah2 ;
|
||||
u32 ethsal3 ;
|
||||
u32 ethsah3 ;
|
||||
u32 ethrbc ;
|
||||
u32 ethrpc ;
|
||||
u32 ethrupc ;
|
||||
u32 ethrfc ;
|
||||
u32 ethtbc ;
|
||||
u32 ethgpf ;
|
||||
u32 eth_u9 [50] ; // Reserved.
|
||||
u32 ethmac1 ;
|
||||
u32 ethmac2 ;
|
||||
u32 ethipgt ;
|
||||
u32 ethipgr ;
|
||||
u32 ethclrt ;
|
||||
u32 ethmaxf ;
|
||||
u32 eth_u10 ; // Reserved.
|
||||
u32 ethmtest ;
|
||||
u32 miimcfg ;
|
||||
u32 miimcmd ;
|
||||
u32 miimaddr ;
|
||||
u32 miimwtd ;
|
||||
u32 miimrdd ;
|
||||
u32 miimind ;
|
||||
u32 eth_u11 ; // Reserved.
|
||||
u32 eth_u12 ; // Reserved.
|
||||
u32 ethcfsa0 ;
|
||||
u32 ethcfsa1 ;
|
||||
u32 ethcfsa2 ;
|
||||
} volatile *ETH_t;
|
||||
|
||||
enum
|
||||
{
|
||||
ETHINTFC_en_b = 0,
|
||||
ETHINTFC_en_m = 0x00000001,
|
||||
ETHINTFC_its_b = 1,
|
||||
ETHINTFC_its_m = 0x00000002,
|
||||
ETHINTFC_rip_b = 2,
|
||||
ETHINTFC_rip_m = 0x00000004,
|
||||
ETHINTFC_jam_b = 3,
|
||||
ETHINTFC_jam_m = 0x00000008,
|
||||
ETHINTFC_ovr_b = 4,
|
||||
ETHINTFC_ovr_m = 0x00000010,
|
||||
ETHINTFC_und_b = 5,
|
||||
ETHINTFC_und_m = 0x00000020,
|
||||
ETHINTFC_iom_b = 6,
|
||||
ETHINTFC_iom_m = 0x000000c0,
|
||||
|
||||
ETHFIFOTT_tth_b = 0,
|
||||
ETHFIFOTT_tth_m = 0x0000007f,
|
||||
|
||||
ETHARC_pro_b = 0,
|
||||
ETHARC_pro_m = 0x00000001,
|
||||
ETHARC_am_b = 1,
|
||||
ETHARC_am_m = 0x00000002,
|
||||
ETHARC_afm_b = 2,
|
||||
ETHARC_afm_m = 0x00000004,
|
||||
ETHARC_ab_b = 3,
|
||||
ETHARC_ab_m = 0x00000008,
|
||||
|
||||
ETHSAL_byte5_b = 0,
|
||||
ETHSAL_byte5_m = 0x000000ff,
|
||||
ETHSAL_byte4_b = 8,
|
||||
ETHSAL_byte4_m = 0x0000ff00,
|
||||
ETHSAL_byte3_b = 16,
|
||||
ETHSAL_byte3_m = 0x00ff0000,
|
||||
ETHSAL_byte2_b = 24,
|
||||
ETHSAL_byte2_m = 0xff000000,
|
||||
|
||||
ETHSAH_byte1_b = 0,
|
||||
ETHSAH_byte1_m = 0x000000ff,
|
||||
ETHSAH_byte0_b = 8,
|
||||
ETHSAH_byte0_m = 0x0000ff00,
|
||||
|
||||
ETHGPF_ptv_b = 0,
|
||||
ETHGPF_ptv_m = 0x0000ffff,
|
||||
|
||||
ETHPFS_pfd_b = 0,
|
||||
ETHPFS_pfd_m = 0x00000001,
|
||||
|
||||
ETHCFSA0_cfsa4_b = 0,
|
||||
ETHCFSA0_cfsa4_m = 0x000000ff,
|
||||
ETHCFSA0_cfsa5_b = 8,
|
||||
ETHCFSA0_cfsa5_m = 0x0000ff00,
|
||||
|
||||
ETHCFSA1_cfsa2_b = 0,
|
||||
ETHCFSA1_cfsa2_m = 0x000000ff,
|
||||
ETHCFSA1_cfsa3_b = 8,
|
||||
ETHCFSA1_cfsa3_m = 0x0000ff00,
|
||||
|
||||
ETHCFSA2_cfsa0_b = 0,
|
||||
ETHCFSA2_cfsa0_m = 0x000000ff,
|
||||
ETHCFSA2_cfsa1_b = 8,
|
||||
ETHCFSA2_cfsa1_m = 0x0000ff00,
|
||||
|
||||
ETHMAC1_re_b = 0,
|
||||
ETHMAC1_re_m = 0x00000001,
|
||||
ETHMAC1_paf_b = 1,
|
||||
ETHMAC1_paf_m = 0x00000002,
|
||||
ETHMAC1_rfc_b = 2,
|
||||
ETHMAC1_rfc_m = 0x00000004,
|
||||
ETHMAC1_tfc_b = 3,
|
||||
ETHMAC1_tfc_m = 0x00000008,
|
||||
ETHMAC1_lb_b = 4,
|
||||
ETHMAC1_lb_m = 0x00000010,
|
||||
ETHMAC1_mr_b = 31,
|
||||
ETHMAC1_mr_m = 0x80000000,
|
||||
|
||||
ETHMAC2_fd_b = 0,
|
||||
ETHMAC2_fd_m = 0x00000001,
|
||||
ETHMAC2_flc_b = 1,
|
||||
ETHMAC2_flc_m = 0x00000002,
|
||||
ETHMAC2_hfe_b = 2,
|
||||
ETHMAC2_hfe_m = 0x00000004,
|
||||
ETHMAC2_dc_b = 3,
|
||||
ETHMAC2_dc_m = 0x00000008,
|
||||
ETHMAC2_cen_b = 4,
|
||||
ETHMAC2_cen_m = 0x00000010,
|
||||
ETHMAC2_pe_b = 5,
|
||||
ETHMAC2_pe_m = 0x00000020,
|
||||
ETHMAC2_vpe_b = 6,
|
||||
ETHMAC2_vpe_m = 0x00000040,
|
||||
ETHMAC2_ape_b = 7,
|
||||
ETHMAC2_ape_m = 0x00000080,
|
||||
ETHMAC2_ppe_b = 8,
|
||||
ETHMAC2_ppe_m = 0x00000100,
|
||||
ETHMAC2_lpe_b = 9,
|
||||
ETHMAC2_lpe_m = 0x00000200,
|
||||
ETHMAC2_nb_b = 12,
|
||||
ETHMAC2_nb_m = 0x00001000,
|
||||
ETHMAC2_bp_b = 13,
|
||||
ETHMAC2_bp_m = 0x00002000,
|
||||
ETHMAC2_ed_b = 14,
|
||||
ETHMAC2_ed_m = 0x00004000,
|
||||
|
||||
ETHIPGT_ipgt_b = 0,
|
||||
ETHIPGT_ipgt_m = 0x0000007f,
|
||||
|
||||
ETHIPGR_ipgr2_b = 0,
|
||||
ETHIPGR_ipgr2_m = 0x0000007f,
|
||||
ETHIPGR_ipgr1_b = 8,
|
||||
ETHIPGR_ipgr1_m = 0x00007f00,
|
||||
|
||||
ETHCLRT_maxret_b = 0,
|
||||
ETHCLRT_maxret_m = 0x0000000f,
|
||||
ETHCLRT_colwin_b = 8,
|
||||
ETHCLRT_colwin_m = 0x00003f00,
|
||||
|
||||
ETHMAXF_maxf_b = 0,
|
||||
ETHMAXF_maxf_m = 0x0000ffff,
|
||||
|
||||
ETHMTEST_tb_b = 2,
|
||||
ETHMTEST_tb_m = 0x00000004,
|
||||
|
||||
ETHMCP_div_b = 0,
|
||||
ETHMCP_div_m = 0x000000ff,
|
||||
|
||||
MIIMCFG_rsv_b = 0,
|
||||
MIIMCFG_rsv_m = 0x0000000c,
|
||||
|
||||
MIIMCMD_rd_b = 0,
|
||||
MIIMCMD_rd_m = 0x00000001,
|
||||
MIIMCMD_scn_b = 1,
|
||||
MIIMCMD_scn_m = 0x00000002,
|
||||
|
||||
MIIMADDR_regaddr_b = 0,
|
||||
MIIMADDR_regaddr_m = 0x0000001f,
|
||||
MIIMADDR_phyaddr_b = 8,
|
||||
MIIMADDR_phyaddr_m = 0x00001f00,
|
||||
|
||||
MIIMWTD_wdata_b = 0,
|
||||
MIIMWTD_wdata_m = 0x0000ffff,
|
||||
|
||||
MIIMRDD_rdata_b = 0,
|
||||
MIIMRDD_rdata_m = 0x0000ffff,
|
||||
|
||||
MIIMIND_bsy_b = 0,
|
||||
MIIMIND_bsy_m = 0x00000001,
|
||||
MIIMIND_scn_b = 1,
|
||||
MIIMIND_scn_m = 0x00000002,
|
||||
MIIMIND_nv_b = 2,
|
||||
MIIMIND_nv_m = 0x00000004,
|
||||
|
||||
} ;
|
||||
|
||||
/*
|
||||
* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
|
||||
*/
|
||||
enum
|
||||
{
|
||||
ETHRX_fd_b = 0,
|
||||
ETHRX_fd_m = 0x00000001,
|
||||
ETHRX_ld_b = 1,
|
||||
ETHRX_ld_m = 0x00000002,
|
||||
ETHRX_rok_b = 2,
|
||||
ETHRX_rok_m = 0x00000004,
|
||||
ETHRX_fm_b = 3,
|
||||
ETHRX_fm_m = 0x00000008,
|
||||
ETHRX_mp_b = 4,
|
||||
ETHRX_mp_m = 0x00000010,
|
||||
ETHRX_bp_b = 5,
|
||||
ETHRX_bp_m = 0x00000020,
|
||||
ETHRX_vlt_b = 6,
|
||||
ETHRX_vlt_m = 0x00000040,
|
||||
ETHRX_cf_b = 7,
|
||||
ETHRX_cf_m = 0x00000080,
|
||||
ETHRX_ovr_b = 8,
|
||||
ETHRX_ovr_m = 0x00000100,
|
||||
ETHRX_crc_b = 9,
|
||||
ETHRX_crc_m = 0x00000200,
|
||||
ETHRX_cv_b = 10,
|
||||
ETHRX_cv_m = 0x00000400,
|
||||
ETHRX_db_b = 11,
|
||||
ETHRX_db_m = 0x00000800,
|
||||
ETHRX_le_b = 12,
|
||||
ETHRX_le_m = 0x00001000,
|
||||
ETHRX_lor_b = 13,
|
||||
ETHRX_lor_m = 0x00002000,
|
||||
ETHRX_ces_b = 14,
|
||||
ETHRX_ces_m = 0x00004000,
|
||||
ETHRX_length_b = 16,
|
||||
ETHRX_length_m = 0xffff0000,
|
||||
|
||||
ETHTX_fd_b = 0,
|
||||
ETHTX_fd_m = 0x00000001,
|
||||
ETHTX_ld_b = 1,
|
||||
ETHTX_ld_m = 0x00000002,
|
||||
ETHTX_oen_b = 2,
|
||||
ETHTX_oen_m = 0x00000004,
|
||||
ETHTX_pen_b = 3,
|
||||
ETHTX_pen_m = 0x00000008,
|
||||
ETHTX_cen_b = 4,
|
||||
ETHTX_cen_m = 0x00000010,
|
||||
ETHTX_hen_b = 5,
|
||||
ETHTX_hen_m = 0x00000020,
|
||||
ETHTX_tok_b = 6,
|
||||
ETHTX_tok_m = 0x00000040,
|
||||
ETHTX_mp_b = 7,
|
||||
ETHTX_mp_m = 0x00000080,
|
||||
ETHTX_bp_b = 8,
|
||||
ETHTX_bp_m = 0x00000100,
|
||||
ETHTX_und_b = 9,
|
||||
ETHTX_und_m = 0x00000200,
|
||||
ETHTX_of_b = 10,
|
||||
ETHTX_of_m = 0x00000400,
|
||||
ETHTX_ed_b = 11,
|
||||
ETHTX_ed_m = 0x00000800,
|
||||
ETHTX_ec_b = 12,
|
||||
ETHTX_ec_m = 0x00001000,
|
||||
ETHTX_lc_b = 13,
|
||||
ETHTX_lc_m = 0x00002000,
|
||||
ETHTX_td_b = 14,
|
||||
ETHTX_td_m = 0x00004000,
|
||||
ETHTX_crc_b = 15,
|
||||
ETHTX_crc_m = 0x00008000,
|
||||
ETHTX_le_b = 16,
|
||||
ETHTX_le_m = 0x00010000,
|
||||
ETHTX_cc_b = 17,
|
||||
ETHTX_cc_m = 0x001E0000,
|
||||
} ;
|
||||
|
||||
#endif // __IDT_ETH_H__
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
#ifndef __IDT_ETH_V_H__
|
||||
#define __IDT_ETH_V_H__
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Ethernet register definition.
|
||||
*
|
||||
* File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
|
||||
*
|
||||
* Author : Allen.Stichter@idt.com
|
||||
* Date : 20020605
|
||||
* Update :
|
||||
* $Log: eth.h,v $
|
||||
* Revision 1.3 2002/06/06 18:34:04 astichte
|
||||
* Added XXX_PhysicalAddress and XXX_VirtualAddress
|
||||
*
|
||||
* Revision 1.2 2002/06/05 18:19:46 astichte
|
||||
* Added
|
||||
*
|
||||
* Revision 1.1 2002/05/29 17:33:22 sysarch
|
||||
* jba File moved from vcode/include/idt/acacia
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <asm/rc32434/eth.h>
|
||||
|
||||
#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
|
||||
#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
|
||||
#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
|
||||
#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
|
||||
#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
|
||||
#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
|
||||
#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
|
||||
#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
|
||||
#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
|
||||
#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
|
||||
#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
|
||||
|
||||
#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
|
||||
|
||||
#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
|
||||
#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
|
||||
#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
|
||||
#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
|
||||
#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
|
||||
#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
|
||||
#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
|
||||
#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
|
||||
#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
|
||||
#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
|
||||
#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
|
||||
#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
|
||||
#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
|
||||
#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
|
||||
#endif // __IDT_ETH_V_H__
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
122
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/gpio.h
Normal file
122
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/gpio.h
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* GPIO register definition.
|
||||
*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
* Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
|
||||
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RC32434_GPIO_H_
|
||||
#define _RC32434_GPIO_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct rb500_gpio_reg {
|
||||
u32 gpiofunc; /* GPIO Function Register
|
||||
* gpiofunc[x]==0 bit = gpio
|
||||
* func[x]==1 bit = altfunc
|
||||
*/
|
||||
u32 gpiocfg; /* GPIO Configuration Register
|
||||
* gpiocfg[x]==0 bit = input
|
||||
* gpiocfg[x]==1 bit = output
|
||||
*/
|
||||
u32 gpiod; /* GPIO Data Register
|
||||
* gpiod[x] read/write gpio pinX status
|
||||
*/
|
||||
u32 gpioilevel; /* GPIO Interrupt Status Register
|
||||
* interrupt level (see gpioistat)
|
||||
*/
|
||||
u32 gpioistat; /* Gpio Interrupt Status Register
|
||||
* istat[x] = (gpiod[x] == level[x])
|
||||
* cleared in ISR (STICKY bits)
|
||||
*/
|
||||
u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
|
||||
};
|
||||
|
||||
/* UART GPIO signals */
|
||||
#define RC32434_UART0_SOUT (1 << 0)
|
||||
#define RC32434_UART0_SIN (1 << 1)
|
||||
#define RC32434_UART0_RTS (1 << 2)
|
||||
#define RC32434_UART0_CTS (1 << 3)
|
||||
|
||||
/* M & P bus GPIO signals */
|
||||
#define RC32434_MP_BIT_22 (1 << 4)
|
||||
#define RC32434_MP_BIT_23 (1 << 5)
|
||||
#define RC32434_MP_BIT_24 (1 << 6)
|
||||
#define RC32434_MP_BIT_25 (1 << 7)
|
||||
|
||||
/* CPU GPIO signals */
|
||||
#define RC32434_CPU_GPIO (1 << 8)
|
||||
|
||||
/* Reserved GPIO signals */
|
||||
#define RC32434_AF_SPARE_6 (1 << 9)
|
||||
#define RC32434_AF_SPARE_4 (1 << 10)
|
||||
#define RC32434_AF_SPARE_3 (1 << 11)
|
||||
#define RC32434_AF_SPARE_2 (1 << 12)
|
||||
|
||||
/* PCI messaging unit */
|
||||
#define RC32434_PCI_MSU_GPIO (1 << 13)
|
||||
|
||||
extern int rb500_gpio_get_value(unsigned gpio);
|
||||
extern void rb500_gpio_set_value(unsigned gpio, int value);
|
||||
extern int rb500_gpio_direction_input(unsigned gpio);
|
||||
extern int rb500_gpio_direction_output(unsigned gpio, int value);
|
||||
extern void rb500_gpio_set_int_level(unsigned gpio, int value);
|
||||
extern int rb500_gpio_get_int_level(unsigned gpio);
|
||||
extern void rb500_gpio_set_int_status(unsigned gpio, int value);
|
||||
extern int rb500_gpio_get_int_status(unsigned gpio);
|
||||
extern void rb500_gpio_set_func(unsigned gpio, int value);
|
||||
extern int rb500_gpio_get_func(unsigned gpio);
|
||||
|
||||
|
||||
/* Wrappers for the arch-neutral GPIO API */
|
||||
|
||||
static inline int gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
/* Not yet implemented */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void gpio_free(unsigned gpio)
|
||||
{
|
||||
/* Not yet implemented */
|
||||
}
|
||||
|
||||
static inline int gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
return rb500_gpio_direction_input(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_direction_output(unsigned gpio, int value)
|
||||
{
|
||||
return rb500_gpio_direction_output(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
return rb500_gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
rb500_gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return gpio;
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* For cansleep */
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* _RC32434_GPIO_H_ */
|
||||
@@ -0,0 +1,76 @@
|
||||
#ifndef __IDT_INTEG_H__
|
||||
#define __IDT_INTEG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Copyright 2002 Integrated Device Technology, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* System Integrity register definition.
|
||||
*
|
||||
* File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
|
||||
*
|
||||
* Author : ryan.holmQVist@idt.com
|
||||
* Date : 20011005
|
||||
* Update :
|
||||
* $Log: integ.h,v $
|
||||
* Revision 1.3 2002/06/06 18:34:04 astichte
|
||||
* Added XXX_PhysicalAddress and XXX_VirtualAddress
|
||||
*
|
||||
* Revision 1.2 2002/06/05 18:32:33 astichte
|
||||
* Removed IDTField
|
||||
*
|
||||
* Revision 1.1 2002/05/29 17:33:22 sysarch
|
||||
* jba File moved from vcode/include/idt/acacia
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
enum
|
||||
{
|
||||
INTEG0_PhysicalAddress = 0x18030000,
|
||||
INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
|
||||
|
||||
INTEG0_VirtualAddress = 0xb8030000,
|
||||
INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
|
||||
} ;
|
||||
|
||||
// if you are looing for CEA, try rst.h
|
||||
typedef struct
|
||||
{
|
||||
u32 filler [0xc] ; // 0x30 bytes unused.
|
||||
u32 errcs ; // sticky use ERRCS_
|
||||
u32 wtcount ; // Watchdog timer count reg.
|
||||
u32 wtcompare ; // Watchdog timer timeout value.
|
||||
u32 wtc ; // Watchdog timer control. use WTC_
|
||||
} volatile *INTEG_t ;
|
||||
|
||||
enum
|
||||
{
|
||||
ERRCS_wto_b = 0, // In INTEG_t -> errcs
|
||||
ERRCS_wto_m = 0x00000001,
|
||||
ERRCS_wne_b = 1, // In INTEG_t -> errcs
|
||||
ERRCS_wne_m = 0x00000002,
|
||||
ERRCS_ucw_b = 2, // In INTEG_t -> errcs
|
||||
ERRCS_ucw_m = 0x00000004,
|
||||
ERRCS_ucr_b = 3, // In INTEG_t -> errcs
|
||||
ERRCS_ucr_m = 0x00000008,
|
||||
ERRCS_upw_b = 4, // In INTEG_t -> errcs
|
||||
ERRCS_upw_m = 0x00000010,
|
||||
ERRCS_upr_b = 5, // In INTEG_t -> errcs
|
||||
ERRCS_upr_m = 0x00000020,
|
||||
ERRCS_udw_b = 6, // In INTEG_t -> errcs
|
||||
ERRCS_udw_m = 0x00000040,
|
||||
ERRCS_udr_b = 7, // In INTEG_t -> errcs
|
||||
ERRCS_udr_m = 0x00000080,
|
||||
ERRCS_sae_b = 8, // In INTEG_t -> errcs
|
||||
ERRCS_sae_m = 0x00000100,
|
||||
ERRCS_wre_b = 9, // In INTEG_t -> errcs
|
||||
ERRCS_wre_m = 0x00000200,
|
||||
|
||||
WTC_en_b = 0, // In INTEG_t -> wtc
|
||||
WTC_en_m = 0x00000001,
|
||||
WTC_to_b = 1, // In INTEG_t -> wtc
|
||||
WTC_to_m = 0x00000002,
|
||||
} ;
|
||||
|
||||
#endif // __IDT_INTEG_H__
|
||||
@@ -0,0 +1,7 @@
|
||||
#ifndef __ASM_MACH_MIPS_IRQ_H
|
||||
#define __ASM_MACH_MIPS_IRQ_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_MIPS_IRQ_H */
|
||||
692
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/pci.h
Normal file
692
target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/pci.h
Normal file
@@ -0,0 +1,692 @@
|
||||
/**************************************************************************
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PCI register definitio
|
||||
*
|
||||
* Copyright 2004 IDT Inc. (rischelp@idt.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
**************************************************************************
|
||||
* May 2004 rkt, neb.
|
||||
*
|
||||
* Initial Release
|
||||
*
|
||||
*
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __IDT_PCI_H__
|
||||
#define __IDT_PCI_H__
|
||||
|
||||
enum
|
||||
{
|
||||
PCI0_PhysicalAddress = 0x18080000,
|
||||
PCI_PhysicalAddress = PCI0_PhysicalAddress,
|
||||
|
||||
PCI0_VirtualAddress = 0xB8080000,
|
||||
PCI_VirtualAddress = PCI0_VirtualAddress,
|
||||
} ;
|
||||
|
||||
enum
|
||||
{
|
||||
PCI_LbaCount = 4, // Local base addresses.
|
||||
} ;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 a ; // Address.
|
||||
u32 c ; // Control.
|
||||
u32 m ; // mapping.
|
||||
} PCI_Map_s ;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 pcic ;
|
||||
u32 pcis ;
|
||||
u32 pcism ;
|
||||
u32 pcicfga ;
|
||||
u32 pcicfgd ;
|
||||
PCI_Map_s pcilba [PCI_LbaCount] ;
|
||||
u32 pcidac ;
|
||||
u32 pcidas ;
|
||||
u32 pcidasm ;
|
||||
u32 pcidad ;
|
||||
u32 pcidma8c ;
|
||||
u32 pcidma9c ;
|
||||
u32 pcitc ;
|
||||
} volatile *PCI_t ;
|
||||
|
||||
// PCI messaging unit.
|
||||
enum
|
||||
{
|
||||
PCIM_Count = 2,
|
||||
} ;
|
||||
typedef struct
|
||||
{
|
||||
u32 pciim [PCIM_Count] ;
|
||||
u32 pciom [PCIM_Count] ;
|
||||
u32 pciid ;
|
||||
u32 pciiic ;
|
||||
u32 pciiim ;
|
||||
u32 pciiod ;
|
||||
u32 pciioic ;
|
||||
u32 pciioim ;
|
||||
} volatile *PCIM_t ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Control Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum
|
||||
{
|
||||
PCIC_en_b = 0,
|
||||
PCIC_en_m = 0x00000001,
|
||||
PCIC_tnr_b = 1,
|
||||
PCIC_tnr_m = 0x00000002,
|
||||
PCIC_sce_b = 2,
|
||||
PCIC_sce_m = 0x00000004,
|
||||
PCIC_ien_b = 3,
|
||||
PCIC_ien_m = 0x00000008,
|
||||
PCIC_aaa_b = 4,
|
||||
PCIC_aaa_m = 0x00000010,
|
||||
PCIC_eap_b = 5,
|
||||
PCIC_eap_m = 0x00000020,
|
||||
PCIC_pcim_b = 6,
|
||||
PCIC_pcim_m = 0x000001c0,
|
||||
PCIC_pcim_disabled_v = 0,
|
||||
PCIC_pcim_tnr_v = 1, // Satellite - target not ready
|
||||
PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
|
||||
PCIC_pcim_extern_v = 3, // Host - external arbiter.
|
||||
PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
|
||||
PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
|
||||
PCIC_pcim_reserved6_v = 6,
|
||||
PCIC_pcim_reserved7_v = 7,
|
||||
PCIC_igm_b = 9,
|
||||
PCIC_igm_m = 0x00000200,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Status Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCIS_eed_b = 0,
|
||||
PCIS_eed_m = 0x00000001,
|
||||
PCIS_wr_b = 1,
|
||||
PCIS_wr_m = 0x00000002,
|
||||
PCIS_nmi_b = 2,
|
||||
PCIS_nmi_m = 0x00000004,
|
||||
PCIS_ii_b = 3,
|
||||
PCIS_ii_m = 0x00000008,
|
||||
PCIS_cwe_b = 4,
|
||||
PCIS_cwe_m = 0x00000010,
|
||||
PCIS_cre_b = 5,
|
||||
PCIS_cre_m = 0x00000020,
|
||||
PCIS_mdpe_b = 6,
|
||||
PCIS_mdpe_m = 0x00000040,
|
||||
PCIS_sta_b = 7,
|
||||
PCIS_sta_m = 0x00000080,
|
||||
PCIS_rta_b = 8,
|
||||
PCIS_rta_m = 0x00000100,
|
||||
PCIS_rma_b = 9,
|
||||
PCIS_rma_m = 0x00000200,
|
||||
PCIS_sse_b = 10,
|
||||
PCIS_sse_m = 0x00000400,
|
||||
PCIS_ose_b = 11,
|
||||
PCIS_ose_m = 0x00000800,
|
||||
PCIS_pe_b = 12,
|
||||
PCIS_pe_m = 0x00001000,
|
||||
PCIS_tae_b = 13,
|
||||
PCIS_tae_m = 0x00002000,
|
||||
PCIS_rle_b = 14,
|
||||
PCIS_rle_m = 0x00004000,
|
||||
PCIS_bme_b = 15,
|
||||
PCIS_bme_m = 0x00008000,
|
||||
PCIS_prd_b = 16,
|
||||
PCIS_prd_m = 0x00010000,
|
||||
PCIS_rip_b = 17,
|
||||
PCIS_rip_m = 0x00020000,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Status Mask Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCISM_eed_b = 0,
|
||||
PCISM_eed_m = 0x00000001,
|
||||
PCISM_wr_b = 1,
|
||||
PCISM_wr_m = 0x00000002,
|
||||
PCISM_nmi_b = 2,
|
||||
PCISM_nmi_m = 0x00000004,
|
||||
PCISM_ii_b = 3,
|
||||
PCISM_ii_m = 0x00000008,
|
||||
PCISM_cwe_b = 4,
|
||||
PCISM_cwe_m = 0x00000010,
|
||||
PCISM_cre_b = 5,
|
||||
PCISM_cre_m = 0x00000020,
|
||||
PCISM_mdpe_b = 6,
|
||||
PCISM_mdpe_m = 0x00000040,
|
||||
PCISM_sta_b = 7,
|
||||
PCISM_sta_m = 0x00000080,
|
||||
PCISM_rta_b = 8,
|
||||
PCISM_rta_m = 0x00000100,
|
||||
PCISM_rma_b = 9,
|
||||
PCISM_rma_m = 0x00000200,
|
||||
PCISM_sse_b = 10,
|
||||
PCISM_sse_m = 0x00000400,
|
||||
PCISM_ose_b = 11,
|
||||
PCISM_ose_m = 0x00000800,
|
||||
PCISM_pe_b = 12,
|
||||
PCISM_pe_m = 0x00001000,
|
||||
PCISM_tae_b = 13,
|
||||
PCISM_tae_m = 0x00002000,
|
||||
PCISM_rle_b = 14,
|
||||
PCISM_rle_m = 0x00004000,
|
||||
PCISM_bme_b = 15,
|
||||
PCISM_bme_m = 0x00008000,
|
||||
PCISM_prd_b = 16,
|
||||
PCISM_prd_m = 0x00010000,
|
||||
PCISM_rip_b = 17,
|
||||
PCISM_rip_m = 0x00020000,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Configuration Address Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCICFGA_reg_b = 2,
|
||||
PCICFGA_reg_m = 0x000000fc,
|
||||
PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
|
||||
PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
|
||||
PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
|
||||
PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
|
||||
PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
|
||||
PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
|
||||
PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
|
||||
PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
|
||||
PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
|
||||
PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
|
||||
PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
|
||||
PCICFGA_reg_pba0m_v = 0x48>>2,
|
||||
PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
|
||||
PCICFGA_reg_pba1m_v = 0x50>>2,
|
||||
PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
|
||||
PCICFGA_reg_pba2m_v = 0x58>>2,
|
||||
PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
|
||||
PCICFGA_reg_pba3m_v = 0x60>>2,
|
||||
PCICFGA_reg_pmgt_v = 0x64>>2,
|
||||
PCICFGA_func_b = 8,
|
||||
PCICFGA_func_m = 0x00000700,
|
||||
PCICFGA_dev_b = 11,
|
||||
PCICFGA_dev_m = 0x0000f800,
|
||||
PCICFGA_dev_internal_v = 0,
|
||||
PCICFGA_bus_b = 16,
|
||||
PCICFGA_bus_m = 0x00ff0000,
|
||||
PCICFGA_bus_type0_v = 0, //local bus
|
||||
PCICFGA_en_b = 31, // read only
|
||||
PCICFGA_en_m = 0x80000000,
|
||||
} ;
|
||||
|
||||
enum {
|
||||
PCFGID_vendor_b = 0,
|
||||
PCFGID_vendor_m = 0x0000ffff,
|
||||
PCFGID_vendor_IDT_v = 0x111d,
|
||||
PCFGID_device_b = 16,
|
||||
PCFGID_device_m = 0xffff0000,
|
||||
PCFGID_device_Korinade_v = 0x0214,
|
||||
|
||||
PCFG04_command_ioena_b = 1,
|
||||
PCFG04_command_ioena_m = 0x00000001,
|
||||
PCFG04_command_memena_b = 2,
|
||||
PCFG04_command_memena_m = 0x00000002,
|
||||
PCFG04_command_bmena_b = 3,
|
||||
PCFG04_command_bmena_m = 0x00000004,
|
||||
PCFG04_command_mwinv_b = 5,
|
||||
PCFG04_command_mwinv_m = 0x00000010,
|
||||
PCFG04_command_parena_b = 7,
|
||||
PCFG04_command_parena_m = 0x00000040,
|
||||
PCFG04_command_serrena_b = 9,
|
||||
PCFG04_command_serrena_m = 0x00000100,
|
||||
PCFG04_command_fastbbena_b = 10,
|
||||
PCFG04_command_fastbbena_m = 0x00000200,
|
||||
PCFG04_status_b = 16,
|
||||
PCFG04_status_m = 0xffff0000,
|
||||
PCFG04_status_66MHz_b = 21, // 66 MHz enable
|
||||
PCFG04_status_66MHz_m = 0x00200000,
|
||||
PCFG04_status_fbb_b = 23,
|
||||
PCFG04_status_fbb_m = 0x00800000,
|
||||
PCFG04_status_mdpe_b = 24,
|
||||
PCFG04_status_mdpe_m = 0x01000000,
|
||||
PCFG04_status_dst_b = 25,
|
||||
PCFG04_status_dst_m = 0x06000000,
|
||||
PCFG04_status_sta_b = 27,
|
||||
PCFG04_status_sta_m = 0x08000000,
|
||||
PCFG04_status_rta_b = 28,
|
||||
PCFG04_status_rta_m = 0x10000000,
|
||||
PCFG04_status_rma_b = 29,
|
||||
PCFG04_status_rma_m = 0x20000000,
|
||||
PCFG04_status_sse_b = 30,
|
||||
PCFG04_status_sse_m = 0x40000000,
|
||||
PCFG04_status_pe_b = 31,
|
||||
PCFG04_status_pe_m = 0x40000000,
|
||||
|
||||
PCFG08_revId_b = 0,
|
||||
PCFG08_revId_m = 0x000000ff,
|
||||
PCFG08_classCode_b = 0,
|
||||
PCFG08_classCode_m = 0xffffff00,
|
||||
PCFG08_classCode_bridge_v = 06,
|
||||
PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
|
||||
PCFG0C_cacheline_b = 0,
|
||||
PCFG0C_cacheline_m = 0x000000ff,
|
||||
PCFG0C_masterLatency_b = 8,
|
||||
PCFG0C_masterLatency_m = 0x0000ff00,
|
||||
PCFG0C_headerType_b = 16,
|
||||
PCFG0C_headerType_m = 0x00ff0000,
|
||||
PCFG0C_bist_b = 24,
|
||||
PCFG0C_bist_m = 0xff000000,
|
||||
|
||||
PCIPBA_msi_b = 0,
|
||||
PCIPBA_msi_m = 0x00000001,
|
||||
PCIPBA_p_b = 3,
|
||||
PCIPBA_p_m = 0x00000004,
|
||||
PCIPBA_baddr_b = 8,
|
||||
PCIPBA_baddr_m = 0xffffff00,
|
||||
|
||||
PCFGSS_vendorId_b = 0,
|
||||
PCFGSS_vendorId_m = 0x0000ffff,
|
||||
PCFGSS_id_b = 16,
|
||||
PCFGSS_id_m = 0xffff0000,
|
||||
|
||||
PCFG3C_interruptLine_b = 0,
|
||||
PCFG3C_interruptLine_m = 0x000000ff,
|
||||
PCFG3C_interruptPin_b = 8,
|
||||
PCFG3C_interruptPin_m = 0x0000ff00,
|
||||
PCFG3C_minGrant_b = 16,
|
||||
PCFG3C_minGrant_m = 0x00ff0000,
|
||||
PCFG3C_maxLat_b = 24,
|
||||
PCFG3C_maxLat_m = 0xff000000,
|
||||
|
||||
PCIPBAC_msi_b = 0,
|
||||
PCIPBAC_msi_m = 0x00000001,
|
||||
PCIPBAC_p_b = 1,
|
||||
PCIPBAC_p_m = 0x00000002,
|
||||
PCIPBAC_size_b = 2,
|
||||
PCIPBAC_size_m = 0x0000007c,
|
||||
PCIPBAC_sb_b = 7,
|
||||
PCIPBAC_sb_m = 0x00000080,
|
||||
PCIPBAC_pp_b = 8,
|
||||
PCIPBAC_pp_m = 0x00000100,
|
||||
PCIPBAC_mr_b = 9,
|
||||
PCIPBAC_mr_m = 0x00000600,
|
||||
PCIPBAC_mr_read_v =0, //no prefetching
|
||||
PCIPBAC_mr_readLine_v =1,
|
||||
PCIPBAC_mr_readMult_v =2,
|
||||
PCIPBAC_mrl_b = 11,
|
||||
PCIPBAC_mrl_m = 0x00000800,
|
||||
PCIPBAC_mrm_b = 12,
|
||||
PCIPBAC_mrm_m = 0x00001000,
|
||||
PCIPBAC_trp_b = 13,
|
||||
PCIPBAC_trp_m = 0x00002000,
|
||||
|
||||
PCFG40_trdyTimeout_b = 0,
|
||||
PCFG40_trdyTimeout_m = 0x000000ff,
|
||||
PCFG40_retryLim_b = 8,
|
||||
PCFG40_retryLim_m = 0x0000ff00,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Local Base Address [0|1|2|3] Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
|
||||
PCILBA_baddr_m = 0xffffff00,
|
||||
} ;
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Local Base Address Control Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
|
||||
PCILBAC_msi_m = 0x00000001,
|
||||
PCILBAC_msi_mem_v = 0,
|
||||
PCILBAC_msi_io_v = 1,
|
||||
PCILBAC_size_b = 2, // In pPci->pcilba[i].c
|
||||
PCILBAC_size_m = 0x0000007c,
|
||||
PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
|
||||
PCILBAC_sb_m = 0x00000080,
|
||||
PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
|
||||
PCILBAC_rt_m = 0x00000100,
|
||||
PCILBAC_rt_noprefetch_v = 0, // mem read
|
||||
PCILBAC_rt_prefetch_v = 1, // mem readline
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Local Base Address [0|1|2|3] Mapping Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCILBAM_maddr_b = 8,
|
||||
PCILBAM_maddr_m = 0xffffff00,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Decoupled Access Control Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCIDAC_den_b = 0,
|
||||
PCIDAC_den_m = 0x00000001,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Decoupled Access Status Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCIDAS_d_b = 0,
|
||||
PCIDAS_d_m = 0x00000001,
|
||||
PCIDAS_b_b = 1,
|
||||
PCIDAS_b_m = 0x00000002,
|
||||
PCIDAS_e_b = 2,
|
||||
PCIDAS_e_m = 0x00000004,
|
||||
PCIDAS_ofe_b = 3,
|
||||
PCIDAS_ofe_m = 0x00000008,
|
||||
PCIDAS_off_b = 4,
|
||||
PCIDAS_off_m = 0x00000010,
|
||||
PCIDAS_ife_b = 5,
|
||||
PCIDAS_ife_m = 0x00000020,
|
||||
PCIDAS_iff_b = 6,
|
||||
PCIDAS_iff_m = 0x00000040,
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI DMA Channel 8 Configuration Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum
|
||||
{
|
||||
PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
|
||||
PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
|
||||
PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
|
||||
PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI DMA Channel 9 Configuration Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum
|
||||
{
|
||||
PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
|
||||
PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
|
||||
} ;
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
|
||||
*
|
||||
******************************************************************************/
|
||||
enum {
|
||||
PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
|
||||
PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
|
||||
// These are for reads (DMA channel 8)
|
||||
PCIDMAD_devcmd_mr_v = 0, //memory read
|
||||
PCIDMAD_devcmd_mrl_v = 1, //memory read line
|
||||
PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
|
||||
PCIDMAD_devcmd_ior_v = 3, //I/O read
|
||||
// These are for writes (DMA channel 9)
|
||||
PCIDMAD_devcmd_mw_v = 0, //memory write
|
||||
PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
|
||||
PCIDMAD_devcmd_iow_v = 3, //I/O write
|
||||
|
||||
// Swap byte field applies to both DMA channel 8 and 9
|
||||
PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
|
||||
PCIDMAD_sb_m = 0x01000000, // swap byte field
|
||||
} ;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI Target Control Register
|
||||
*
|
||||
******************************************************************************/
|
||||
enum
|
||||
{
|
||||
PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
|
||||
PCITC_rtimer_m = 0x000000ff,
|
||||
PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
|
||||
PCITC_dtimer_m = 0x0000ff00,
|
||||
PCITC_rdr_b = 18, // In PCITC_t -> pcitc
|
||||
PCITC_rdr_m = 0x00040000,
|
||||
PCITC_ddt_b = 19, // In PCITC_t -> pcitc
|
||||
PCITC_ddt_m = 0x00080000,
|
||||
} ;
|
||||
/*******************************************************************************
|
||||
*
|
||||
* PCI messaging unit [applies to both inbound and outbound registers ]
|
||||
*
|
||||
******************************************************************************/
|
||||
enum
|
||||
{
|
||||
PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
|
||||
PCIM_m0_m = 0x00000001, // inbound or outbound message 0
|
||||
PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
|
||||
PCIM_m1_m = 0x00000002, // inbound or outbound message 1
|
||||
PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
|
||||
PCIM_db_m = 0x00000004, // inbound or outbound doorbell
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PCI_MSG_VirtualAddress 0xB8088010
|
||||
#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
|
||||
#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
|
||||
|
||||
#define PCIM_SHFT 0x6
|
||||
#define PCIM_BIT_LEN 0x7
|
||||
#define PCIM_H_EA 0x3
|
||||
#define PCIM_H_IA_FIX 0x4
|
||||
#define PCIM_H_IA_RR 0x5
|
||||
|
||||
#define PCI_ADDR_START 0x50000000
|
||||
|
||||
#define CPUTOPCI_MEM_WIN 0x02000000
|
||||
#define CPUTOPCI_IO_WIN 0x00100000
|
||||
#define PCILBA_SIZE_SHFT 2
|
||||
#define PCILBA_SIZE_MASK 0x1F
|
||||
#define SIZE_256MB 0x1C
|
||||
#define SIZE_128MB 0x1B
|
||||
#define SIZE_64MB 0x1A
|
||||
#define SIZE_32MB 0x19
|
||||
#define SIZE_16MB 0x18
|
||||
#define SIZE_4MB 0x16
|
||||
#define SIZE_2MB 0x15
|
||||
#define SIZE_1MB 0x14
|
||||
#define KORINA_CONFIG0_ADDR 0x80000000
|
||||
#define KORINA_CONFIG1_ADDR 0x80000004
|
||||
#define KORINA_CONFIG2_ADDR 0x80000008
|
||||
#define KORINA_CONFIG3_ADDR 0x8000000C
|
||||
#define KORINA_CONFIG4_ADDR 0x80000010
|
||||
#define KORINA_CONFIG5_ADDR 0x80000014
|
||||
#define KORINA_CONFIG6_ADDR 0x80000018
|
||||
#define KORINA_CONFIG7_ADDR 0x8000001C
|
||||
#define KORINA_CONFIG8_ADDR 0x80000020
|
||||
#define KORINA_CONFIG9_ADDR 0x80000024
|
||||
#define KORINA_CONFIG10_ADDR 0x80000028
|
||||
#define KORINA_CONFIG11_ADDR 0x8000002C
|
||||
#define KORINA_CONFIG12_ADDR 0x80000030
|
||||
#define KORINA_CONFIG13_ADDR 0x80000034
|
||||
#define KORINA_CONFIG14_ADDR 0x80000038
|
||||
#define KORINA_CONFIG15_ADDR 0x8000003C
|
||||
#define KORINA_CONFIG16_ADDR 0x80000040
|
||||
#define KORINA_CONFIG17_ADDR 0x80000044
|
||||
#define KORINA_CONFIG18_ADDR 0x80000048
|
||||
#define KORINA_CONFIG19_ADDR 0x8000004C
|
||||
#define KORINA_CONFIG20_ADDR 0x80000050
|
||||
#define KORINA_CONFIG21_ADDR 0x80000054
|
||||
#define KORINA_CONFIG22_ADDR 0x80000058
|
||||
#define KORINA_CONFIG23_ADDR 0x8000005C
|
||||
#define KORINA_CONFIG24_ADDR 0x80000060
|
||||
#define KORINA_CONFIG25_ADDR 0x80000064
|
||||
#define KORINA_CMD (PCFG04_command_ioena_m | \
|
||||
PCFG04_command_memena_m | \
|
||||
PCFG04_command_bmena_m | \
|
||||
PCFG04_command_mwinv_m | \
|
||||
PCFG04_command_parena_m | \
|
||||
PCFG04_command_serrena_m )
|
||||
|
||||
#define KORINA_STAT (PCFG04_status_mdpe_m | \
|
||||
PCFG04_status_sta_m | \
|
||||
PCFG04_status_rta_m | \
|
||||
PCFG04_status_rma_m | \
|
||||
PCFG04_status_sse_m | \
|
||||
PCFG04_status_pe_m)
|
||||
|
||||
#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
|
||||
|
||||
#define KORINA_REVID 0
|
||||
#define KORINA_CLASS_CODE 0
|
||||
#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
|
||||
KORINA_REVID)
|
||||
|
||||
#define KORINA_CACHE_LINE_SIZE 4
|
||||
#define KORINA_MASTER_LAT 0x3c
|
||||
#define KORINA_HEADER_TYPE 0
|
||||
#define KORINA_BIST 0
|
||||
|
||||
#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
|
||||
(KORINA_HEADER_TYPE<<16) | \
|
||||
(KORINA_MASTER_LAT<<8) | \
|
||||
KORINA_CACHE_LINE_SIZE )
|
||||
|
||||
#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
|
||||
#define KORINA_BAR1 0x18800001 /* 1 MB IO */
|
||||
#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
|
||||
internal Registers */
|
||||
#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
|
||||
|
||||
#define KORINA_CNFG4 KORINA_BAR0
|
||||
#define KORINA_CNFG5 KORINA_BAR1
|
||||
#define KORINA_CNFG6 KORINA_BAR2
|
||||
#define KORINA_CNFG7 KORINA_BAR3
|
||||
|
||||
#define KORINA_SUBSYS_VENDOR_ID 0x011d
|
||||
#define KORINA_SUBSYSTEM_ID 0x0214
|
||||
#define KORINA_CNFG8 0
|
||||
#define KORINA_CNFG9 0
|
||||
#define KORINA_CNFG10 0
|
||||
#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
|
||||
KORINA_SUBSYSTEM_ID)
|
||||
#define KORINA_INT_LINE 1
|
||||
#define KORINA_INT_PIN 1
|
||||
#define KORINA_MIN_GNT 8
|
||||
#define KORINA_MAX_LAT 0x38
|
||||
#define KORINA_CNFG12 0
|
||||
#define KORINA_CNFG13 0
|
||||
#define KORINA_CNFG14 0
|
||||
#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
|
||||
(KORINA_MIN_GNT<<16) | \
|
||||
(KORINA_INT_PIN<<8) | \
|
||||
KORINA_INT_LINE)
|
||||
#define KORINA_RETRY_LIMIT 0x80
|
||||
#define KORINA_TRDY_LIMIT 0x80
|
||||
#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
|
||||
KORINA_TRDY_LIMIT)
|
||||
#define PCI_PBAxC_R 0x0
|
||||
#define PCI_PBAxC_RL 0x1
|
||||
#define PCI_PBAxC_RM 0x2
|
||||
#define SIZE_SHFT 2
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
|
||||
((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
|
||||
PCIPBAC_pp_m | \
|
||||
(SIZE_128MB<<SIZE_SHFT) | \
|
||||
PCIPBAC_p_m)
|
||||
#else
|
||||
#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
|
||||
((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
|
||||
PCIPBAC_pp_m | \
|
||||
(SIZE_128MB<<SIZE_SHFT) | \
|
||||
PCIPBAC_p_m)
|
||||
#endif
|
||||
#define KORINA_CNFG17 KORINA_PBA0C
|
||||
#define KORINA_PBA0M 0x0
|
||||
#define KORINA_CNFG18 KORINA_PBA0M
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
|
||||
PCIPBAC_msi_m)
|
||||
#else
|
||||
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
|
||||
PCIPBAC_msi_m)
|
||||
#endif
|
||||
#define KORINA_CNFG19 KORINA_PBA1C
|
||||
#define KORINA_PBA1M 0x0
|
||||
#define KORINA_CNFG20 KORINA_PBA1M
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
|
||||
PCIPBAC_msi_m)
|
||||
#else
|
||||
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
|
||||
PCIPBAC_msi_m)
|
||||
#endif
|
||||
#define KORINA_CNFG21 KORINA_PBA2C
|
||||
#define KORINA_PBA2M 0x18000000
|
||||
#define KORINA_CNFG22 KORINA_PBA2M
|
||||
#define KORINA_PBA3C 0
|
||||
#define KORINA_CNFG23 KORINA_PBA3C
|
||||
#define KORINA_PBA3M 0
|
||||
#define KORINA_CNFG24 KORINA_PBA3M
|
||||
|
||||
|
||||
|
||||
#define PCITC_DTIMER_VAL 8
|
||||
#define PCITC_RTIMER_VAL 0x10
|
||||
|
||||
|
||||
|
||||
|
||||
#endif // __IDT_PCI_H__
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2004 IDT Inc.
|
||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#ifndef __MIPS_RB_H__
|
||||
#define __MIPS_RB_H__
|
||||
#include <linux/genhd.h>
|
||||
|
||||
#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
|
||||
#define DEV0BASE 0x010000
|
||||
#define DEV0MASK 0x010004
|
||||
#define DEV0C 0x010008
|
||||
#define DEV0TC 0x01000C
|
||||
#define DEV1BASE 0x010010
|
||||
#define DEV1MASK 0x010014
|
||||
#define DEV1C 0x010018
|
||||
#define DEV1TC 0x01001C
|
||||
#define DEV2BASE 0x010020
|
||||
#define DEV2MASK 0x010024
|
||||
#define DEV2C 0x010028
|
||||
#define DEV2TC 0x01002C
|
||||
#define DEV3BASE 0x010030
|
||||
#define DEV3MASK 0x010034
|
||||
#define DEV3C 0x010038
|
||||
#define DEV3TC 0x01003C
|
||||
#define BTCS 0x010040
|
||||
#define BTCOMPARE 0x010044
|
||||
#define GPIOFUNC 0x050000
|
||||
#define GPIOCFG 0x050004
|
||||
#define GPIOD 0x050008
|
||||
#define GPIOILEVEL 0x05000C
|
||||
#define GPIOISTAT 0x050010
|
||||
#define GPIONMIEN 0x050014
|
||||
#define IMASK6 0x038038
|
||||
|
||||
#define LO_WPX (1 << 0)
|
||||
#define LO_ALE (1 << 1)
|
||||
#define LO_CLE (1 << 2)
|
||||
#define LO_CEX (1 << 3)
|
||||
#define LO_FOFF (1 << 5)
|
||||
#define LO_SPICS (1 << 6)
|
||||
#define LO_ULED (1 << 7)
|
||||
|
||||
typedef enum {
|
||||
FUNC = 0x00,
|
||||
CFG = 0x04,
|
||||
DATA = 0x08,
|
||||
ILEVEL = 0x0c,
|
||||
ISTAT = 0x10,
|
||||
NMIEN = 0x14
|
||||
} gpio_func;
|
||||
|
||||
extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
|
||||
extern unsigned get434Reg(unsigned regOffs);
|
||||
extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
|
||||
extern void gpio_set(gpio_func func, u32 mask, u32 value);
|
||||
extern u32 gpio_get(gpio_func func);
|
||||
|
||||
#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
|
||||
|
||||
struct korina_device {
|
||||
char *name;
|
||||
unsigned char mac[6];
|
||||
struct net_device *dev;
|
||||
};
|
||||
|
||||
struct cf_device {
|
||||
int gpio_pin;
|
||||
void *dev;
|
||||
struct gendisk *gd;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
***************************************************************************
|
||||
* Definitions for IDT RC323434 CPU.
|
||||
*
|
||||
****************************************************************************
|
||||
* Kiran Rao
|
||||
*
|
||||
* Original form
|
||||
****************************************************************************
|
||||
* P. Sadik Oct 08, 2003
|
||||
*
|
||||
* Started revision history
|
||||
* Made IDT_BUS_FREQ a kernel configuration parameter
|
||||
****************************************************************************
|
||||
* P. Sadik Oct 10, 2003
|
||||
*
|
||||
* Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
|
||||
* idt_cpu_freq is used everywhere
|
||||
****************************************************************************
|
||||
* P. Sadik Oct 20, 2003
|
||||
*
|
||||
* Removed RC32434_BASE_BAUD
|
||||
****************************************************************************
|
||||
*/
|
||||
#ifndef _RC32434_H_
|
||||
#define _RC32434_H_
|
||||
|
||||
#include <linux/autoconf.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define RC32434_REG_BASE 0x18000000
|
||||
|
||||
#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
|
||||
|
||||
|
||||
#define IDT_CLOCK_MULT 2
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
/* Interrupt Controller */
|
||||
#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
|
||||
#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
|
||||
#define IC_GROUP_OFFSET 0x0C
|
||||
|
||||
#define NUM_INTR_GROUPS 5
|
||||
/* 16550 UARTs */
|
||||
|
||||
#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
|
||||
#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
|
||||
#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
|
||||
#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
|
||||
#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
|
||||
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
|
||||
#else
|
||||
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
|
||||
#endif
|
||||
|
||||
#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
|
||||
// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
|
||||
|
||||
#define local_readl(addr) __raw_readl(addr)
|
||||
#define local_writel(l,addr) __raw_writel(l,addr)
|
||||
|
||||
/* cpu pipeline flush */
|
||||
static inline void rc32434_sync(void)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static inline void rc32434_sync_udelay(int us)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
udelay(us);
|
||||
}
|
||||
|
||||
static inline void rc32434_sync_delay(int ms)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
mdelay(ms);
|
||||
}
|
||||
|
||||
/*
|
||||
* C access to CLZ and CLO instructions
|
||||
* (count leading zeroes/ones).
|
||||
*/
|
||||
static inline int rc32434_clz(unsigned long val)
|
||||
{
|
||||
int ret;
|
||||
__asm__ volatile (
|
||||
".set\tnoreorder\n\t"
|
||||
".set\tnoat\n\t"
|
||||
".set\tmips32\n\t"
|
||||
"clz\t%0,%1\n\t"
|
||||
".set\tmips0\n\t"
|
||||
".set\tat\n\t"
|
||||
".set\treorder"
|
||||
: "=r" (ret)
|
||||
: "r" (val));
|
||||
|
||||
return ret;
|
||||
}
|
||||
static inline int rc32434_clo(unsigned long val)
|
||||
{
|
||||
int ret;
|
||||
__asm__ volatile (
|
||||
".set\tnoreorder\n\t"
|
||||
".set\tnoat\n\t"
|
||||
".set\tmips32\n\t"
|
||||
"clo\t%0,%1\n\t"
|
||||
".set\tmips0\n\t"
|
||||
".set\tat\n\t"
|
||||
".set\treorder"
|
||||
: "=r" (ret)
|
||||
: "r" (val));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* _RC32434_H_ */
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
#define __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 1
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
||||
Reference in New Issue
Block a user