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octeontx: add linux 5.10 testing kernel support

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Changes from 5.4 to 5.10:
-------------------------
 - patches from 5.4 are all upstream for 5.10 execpt for
   0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch

 - disable block device data integrity (DIF/DIX/T10) in default config
   (CONFIG_BLK_DEV_INTEGRITY)
   This feature is only supported by:
     - Enterprise SAS/SCSI HBAs and Disks
     - Software raid
     - NVMEs with metadata capabilities (most don't have this)
   None of which are part of any octeontx boards.

 - arm64 TEXT_OFFSET (0x80000) has been removed after 5.4
   This will break Uimages with kernel load addresses that aren't 2MiB
   aligned any longer. Resulting in the kernel silently fail to boot.
   For Gatworks newport boards for example, the uimage kernel load
   and execute address is 0x20080000. These need to be changed to
   0x20000000 when running kernels beyond 5.4.

Tested-on: Gateworks Newport GW64xx

Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
This commit is contained in:
Daniel Danzberger
2021-09-13 06:23:29 +02:00
committed by Hauke Mehrtens
parent 0dbe754e43
commit ba59466bf4
3 changed files with 483 additions and 0 deletions
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59
target/linux/octeontx/patches-5.10/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch Normal file
View File

@@ -0,0 +1,59 @@
From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 10 Apr 2019 08:00:47 -0700
Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
GPIO PERST#
Gateworks boards use PLX PEX860x switches where downstream ports
have their PERST# driven from the PEX GPIO.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
+#include <linux/of.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/switchtec.h>
@@ -5625,3 +5626,34 @@ static void apex_pci_fixup_class(struct
}
DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
+
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+/*
+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
+ * as they are used for slots1-7 PERST#
+ */
+static void newport_pciesw_early_fixup(struct pci_dev *dev)
+{
+ u32 dw;
+
+ if (!of_machine_is_compatible("gw,newport"))
+ return;
+
+ if (dev->devfn != 0)
+ return;
+
+ dev_info(&dev->dev, "de-asserting PERST#\n");
+ pci_read_config_dword(dev, 0x62c, &dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_write_config_dword(dev, 0x62c, dw);
+
+ pci_read_config_dword(dev, 0x644, &dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_write_config_dword(dev, 0x644, dw);
+
+ msleep(100);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */