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ssb: Update to latest upstream version of ssb.

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SVN-Revision: 10490
This commit is contained in:
Michael Büsch
2008-02-19 01:24:18 +00:00
parent 7b2430f271
commit c57ca284ce
15 changed files with 577 additions and 766 deletions
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106
target/linux/generic-2.6/files/include/linux/ssb/ssb.h
View File

@@ -15,22 +15,19 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
struct ssb_sprom_r1 {
u16 pci_spid; /* Subsystem Product ID for PCI */
u16 pci_svid; /* Subsystem Vendor ID for PCI */
u16 pci_pid; /* Product ID for PCI */
struct ssb_sprom {
u8 revision;
u8 il0mac[6]; /* MAC address for 802.11b/g */
u8 et0mac[6]; /* MAC address for Ethernet */
u8 et1mac[6]; /* MAC address for 802.11a */
u8 et0phyaddr:5; /* MII address for enet0 */
u8 et1phyaddr:5; /* MII address for enet1 */
u8 et0mdcport:1; /* MDIO for enet0 */
u8 et1mdcport:1; /* MDIO for enet1 */
u8 board_rev; /* Board revision */
u8 country_code:4; /* Country Code */
u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */
u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */
u8 et0phyaddr; /* MII address for enet0 */
u8 et1phyaddr; /* MII address for enet1 */
u8 et0mdcport; /* MDIO for enet0 */
u8 et1mdcport; /* MDIO for enet1 */
u8 board_rev; /* Board revision number from SPROM. */
u8 country_code; /* Country Code */
u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
u16 pa0b0;
u16 pa0b1;
u16 pa0b2;
@@ -41,61 +38,26 @@ struct ssb_sprom_r1 {
u8 gpio1; /* GPIO pin 1 */
u8 gpio2; /* GPIO pin 2 */
u8 gpio3; /* GPIO pin 3 */
u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
u8 itssi_a; /* Idle TSSI Target for A-PHY */
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
u16 boardflags_lo; /* Boardflags (low 16 bits) */
u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */
u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */
u8 oem[8]; /* OEM string (rev 1 only) */
};
struct ssb_sprom_r2 {
u16 boardflags_hi; /* Boardflags (high 16 bits) */
u8 maxpwr_a_lo; /* A-PHY Max Power Low */
u8 maxpwr_a_hi; /* A-PHY Max Power High */
u16 pa1lob0; /* A-PHY PA Low Settings */
u16 pa1lob1; /* A-PHY PA Low Settings */
u16 pa1lob2; /* A-PHY PA Low Settings */
u16 pa1hib0; /* A-PHY PA High Settings */
u16 pa1hib1; /* A-PHY PA High Settings */
u16 pa1hib2; /* A-PHY PA High Settings */
u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */
u8 country_str[2]; /* Two char Country Code */
};
struct ssb_sprom_r3 {
u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */
u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */
u32 ofdmahpo; /* A-PHY OFDM High Power Offset */
u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */
u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */
u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */
u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */
u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */
u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */
u32 ofdmgpo; /* G-PHY OFDM Power Offset */
};
struct ssb_sprom_r4 {
/* TODO */
};
struct ssb_sprom {
u8 revision;
u8 crc;
/* The valid r# fields are selected by the "revision".
* Revision 3 and lower inherit from lower revisions.
*/
union {
/* Antenna gain values for up to 4 antennas
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
* loss in the connectors is bigger than the gain. */
struct {
struct {
struct ssb_sprom_r1 r1;
struct ssb_sprom_r2 r2;
struct ssb_sprom_r3 r3;
};
struct ssb_sprom_r4 r4;
};
s8 a0, a1, a2, a3;
} ghz24; /* 2.4GHz band */
struct {
s8 a0, a1, a2, a3;
} ghz5; /* 5GHz band */
} antenna_gain;
/* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
};
/* Information about the PCB the circuitry is soldered on. */
@@ -270,7 +232,8 @@ struct ssb_bus {
struct ssb_device *mapped_device;
/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
u8 mapped_pcmcia_seg;
/* Lock for core and segment switching. */
/* Lock for core and segment switching.
* On PCMCIA-host busses this is used to protect the whole MMIO access. */
spinlock_t bar_lock;
/* The bus this backplane is running on. */
@@ -288,6 +251,7 @@ struct ssb_bus {
/* ID information about the Chip. */
u16 chip_id;
u16 chip_rev;
u16 sprom_size; /* number of words in sprom */
u8 chip_package;
/* List of devices (cores) on the backplane. */
@@ -402,6 +366,22 @@ static inline void ssb_pcihost_unregister(struct pci_driver *driver)
{
pci_unregister_driver(driver);
}
static inline
void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
{
if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
pci_set_power_state(sdev->bus->host_pci, state);
}
#else
static inline void ssb_pcihost_unregister(struct pci_driver *driver)
{
}
static inline
void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
{
}
#endif /* CONFIG_SSB_PCIHOST */

83
target/linux/generic-2.6/files/include/linux/ssb/ssb_regs.h
View File

@@ -147,6 +147,10 @@
#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */
#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */
#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */
#define SSB_IDLOW_SSBREV_24 0x40000000 /* ?? Found in BCM4328 */
#define SSB_IDLOW_SSBREV_25 0x50000000 /* ?? Not Found yet */
#define SSB_IDLOW_SSBREV_26 0x60000000 /* ?? Found in some BCM4311/2 */
#define SSB_IDLOW_SSBREV_27 0x70000000 /* ?? Found in some BCM4311/2 */
#define SSB_IDHIGH 0x0FFC /* SB Identification High */
#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */
@@ -162,11 +166,16 @@
*/
#define SSB_SPROMSIZE_WORDS 64
#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
#define SSB_SPROMSIZE_WORDS_R123 64
#define SSB_SPROMSIZE_WORDS_R4 220
#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
#define SSB_SPROM_BASE 0x1000
#define SSB_SPROM_REVISION 0x107E
#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
#define SSB_SPROM_REVISION_CRC_SHIFT 8
/* SPROM Revision 1 */
#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
@@ -184,10 +193,10 @@
#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
#define SSB_SPROM1_BINF_CCODE_SHIFT 8
#define SSB_SPROM1_BINF_ANTA 0x3000 /* Available A-PHY antennas */
#define SSB_SPROM1_BINF_ANTA_SHIFT 12
#define SSB_SPROM1_BINF_ANTBG 0xC000 /* Available B-PHY antennas */
#define SSB_SPROM1_BINF_ANTBG_SHIFT 14
#define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
#define SSB_SPROM1_BINF_ANTA_SHIFT 14
#define SSB_SPROM1_PA0B0 0x105E
#define SSB_SPROM1_PA0B1 0x1060
#define SSB_SPROM1_PA0B2 0x1062
@@ -212,10 +221,11 @@
#define SSB_SPROM1_ITSSI_A_SHIFT 8
#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
#define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */
#define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */
#define SSB_SPROM1_AGAIN_BG_SHIFT 8
#define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */
#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
#define SSB_SPROM1_AGAIN_A_SHIFT 8
/* SPROM Revision 2 (inherits from rev 1) */
#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
@@ -232,7 +242,11 @@
#define SSB_SPROM2_OPO_VALUE 0x00FF
#define SSB_SPROM2_OPO_UNUSED 0xFF00
#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
/* SPROM Revision 3 (inherits from rev 2) */
/* SPROM Revision 3 (inherits most data from rev 2) */
#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
#define SSB_SPROM3_ET0MAC 0x1050 /* 6 bytes MAC address for Ethernet ?? */
#define SSB_SPROM3_ET1MAC 0x1050 /* 6 bytes MAC address for 802.11a ?? */
#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
@@ -251,6 +265,57 @@
#define SSB_SPROM3_CCKPO_11M_SHIFT 12
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
/* SPROM Revision 4 */
#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
#define SSB_SPROM4_ET0MAC 0x1018 /* 6 bytes MAC address for Ethernet ?? */
#define SSB_SPROM4_ET1MAC 0x1018 /* 6 bytes MAC address for 802.11a ?? */
#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
#define SSB_SPROM4_AGAIN0_SHIFT 0
#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
#define SSB_SPROM4_AGAIN1_SHIFT 8
#define SSB_SPROM4_AGAIN23 0x1060
#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
#define SSB_SPROM4_AGAIN2_SHIFT 0
#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
#define SSB_SPROM4_AGAIN3_SHIFT 8
#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
#define SSB_SPROM4_ITSSI_BG_SHIFT 8
#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
#define SSB_SPROM4_ITSSI_A_SHIFT 8
#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
#define SSB_SPROM4_GPIOA_P1_SHIFT 8
#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
#define SSB_SPROM4_GPIOB_P3_SHIFT 8
#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
#define SSB_SPROM4_PA0B2 0x1086
#define SSB_SPROM4_PA1B0 0x108E
#define SSB_SPROM4_PA1B1 0x1090
#define SSB_SPROM4_PA1B2 0x1092
/* Values for SSB_SPROM1_BINF_CCODE */
enum {
SSB_SPROM1CCODE_WORLD = 0,