domenico/openwrt_NSS_ACW
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

kernel: bump 4.14 to 4.14.144

Browse Source 
Refreshed all patches.

Altered patches:
- 816-pcie-support-layerscape.patch

Fixes:
- CVE-2019-15030

Compile-tested on: ar71xx, cns3xxx, imx6, x86_64
Runtime-tested on: ar71xx, cns3xxx, imx6

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
This commit is contained in:
Koen Vandeputte
2019-09-18 15:04:48 +02:00
parent 9cae5a8289
commit d14aa19904
8 changed files with 99 additions and 182 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/kernel-version.mk
View File

@@ -6,9 +6,9 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER) KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif endif
LINUX_VERSION-4.14 = .143 LINUX_VERSION-4.14 = .144
LINUX_KERNEL_HASH-4.14.143 = 2534f2f03cb937700a03dd85dcf1cb6e6f46fdd29d489580cc3183d6c0643d93 LINUX_KERNEL_HASH-4.14.144 = cb8b84675ba060b249ffa62de2366d16e842e3edfcb355ebbfb06bf3de03ca54
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1))))))) sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

7
target/linux/ar71xx/patches-4.14/343-MIPS-ath79-Fix-potentially-missed-IRQ-handling-durin.patch
View File

@@ -23,11 +23,9 @@ CC: stable@vger.kernel.org # v3.2+
arch/mips/ath79/irq.c | 12 +++++++++--- arch/mips/ath79/irq.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-) 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 2dfff1f19004..a03a6bcaf6fd 100644
--- a/arch/mips/ath79/irq.c --- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c
@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) @@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(stru
u32 status; u32 status;
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
@@ -52,6 +50,3 @@ index 2dfff1f19004..a03a6bcaf6fd 100644
} }
} }
--
2.17.1

8
target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
View File

@@ -307,7 +307,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
return; return;
--- a/arch/mips/ath79/irq.c --- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c
@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void) @@ -62,6 +62,34 @@ static void ar934x_ip2_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
} }
@@ -342,7 +342,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
{ {
u32 status; u32 status;
@@ -143,7 +171,7 @@ void __init arch_init_irq(void) @@ -149,7 +177,7 @@ void __init arch_init_irq(void)
soc_is_ar913x() || soc_is_ar933x()) { soc_is_ar913x() || soc_is_ar933x()) {
irq_wb_chan2 = 3; irq_wb_chan2 = 3;
irq_wb_chan3 = 2; irq_wb_chan3 = 2;
@@ -351,7 +351,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
irq_wb_chan3 = 2; irq_wb_chan3 = 2;
} }
@@ -154,6 +182,7 @@ void __init arch_init_irq(void) @@ -160,6 +188,7 @@ void __init arch_init_irq(void)
else if (soc_is_ar724x() || else if (soc_is_ar724x() ||
soc_is_ar933x() || soc_is_ar933x() ||
soc_is_ar934x() || soc_is_ar934x() ||
@@ -359,7 +359,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
soc_is_qca955x()) soc_is_qca955x())
misc_is_ar71xx = false; misc_is_ar71xx = false;
else else
@@ -164,6 +193,8 @@ void __init arch_init_irq(void) @@ -170,6 +199,8 @@ void __init arch_init_irq(void)
if (soc_is_ar934x()) if (soc_is_ar934x())
ar934x_ip2_irq_init(); ar934x_ip2_irq_init();

6
target/linux/ar71xx/patches-4.14/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
View File

@@ -291,7 +291,7 @@
return; return;
--- a/arch/mips/ath79/irq.c --- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c
@@ -156,6 +156,87 @@ static void qca955x_irq_init(void) @@ -162,6 +162,87 @@ static void qca955x_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
} }
@@ -379,7 +379,7 @@
void __init arch_init_irq(void) void __init arch_init_irq(void)
{ {
unsigned irq_wb_chan2 = -1; unsigned irq_wb_chan2 = -1;
@@ -183,7 +264,9 @@ void __init arch_init_irq(void) @@ -189,7 +270,9 @@ void __init arch_init_irq(void)
soc_is_ar933x() || soc_is_ar933x() ||
soc_is_ar934x() || soc_is_ar934x() ||
soc_is_qca953x() || soc_is_qca953x() ||
@@ -390,7 +390,7 @@
misc_is_ar71xx = false; misc_is_ar71xx = false;
else else
BUG(); BUG();
@@ -197,4 +280,6 @@ void __init arch_init_irq(void) @@ -203,4 +286,6 @@ void __init arch_init_irq(void)
qca953x_irq_init(); qca953x_irq_init();
else if (soc_is_qca955x()) else if (soc_is_qca955x())
qca955x_irq_init(); qca955x_irq_init();

10
target/linux/ar71xx/patches-4.14/630-MIPS-ath79-fix-chained-irq-disable.patch
View File

@@ -10,7 +10,7 @@
static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
{ {
u32 status; u32 status;
@@ -50,8 +53,7 @@ static void ar934x_ip2_irq_init(void) @@ -56,8 +59,7 @@ static void ar934x_ip2_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE; for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
@@ -20,7 +20,7 @@
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
} }
@@ -79,7 +81,7 @@ static void qca953x_irq_init(void) @@ -85,7 +87,7 @@ static void qca953x_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE; for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
@@ -29,7 +29,7 @@
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
} }
@@ -143,15 +145,13 @@ static void qca955x_irq_init(void) @@ -149,15 +151,13 @@ static void qca955x_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE; for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
@@ -47,7 +47,7 @@
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
} }
@@ -222,13 +222,13 @@ static void qca956x_irq_init(void) @@ -228,13 +228,13 @@ static void qca956x_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE; for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
@@ -63,7 +63,7 @@
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
@@ -237,12 +237,40 @@ static void qca956x_irq_init(void) @@ -243,12 +243,40 @@ static void qca956x_irq_init(void)
late_time_init = &qca956x_enable_timer_cb; late_time_init = &qca956x_enable_timer_cb;
} }

4
target/linux/ar71xx/patches-4.14/952-qca955x-enable-ddr-wb-flush.patch
View File

@@ -11,7 +11,7 @@
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
--- a/arch/mips/ath79/irq.c --- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c
@@ -99,12 +99,12 @@ static void qca955x_ip2_irq_dispatch(str @@ -105,12 +105,12 @@ static void qca955x_ip2_irq_dispatch(str
} }
if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
@@ -26,7 +26,7 @@
generic_handle_irq(ATH79_IP2_IRQ(1)); generic_handle_irq(ATH79_IP2_IRQ(1));
} }
} }
@@ -124,17 +124,17 @@ static void qca955x_ip3_irq_dispatch(str @@ -130,17 +130,17 @@ static void qca955x_ip3_irq_dispatch(str
} }
if (status & QCA955X_EXT_INT_USB1) { if (status & QCA955X_EXT_INT_USB1) {

4
target/linux/generic/hack-4.14/204-module_strip.patch
View File

@@ -114,7 +114,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
config MODULES_TREE_LOOKUP config MODULES_TREE_LOOKUP
--- a/kernel/module.c --- a/kernel/module.c
+++ b/kernel/module.c +++ b/kernel/module.c
@@ -3008,9 +3008,11 @@ static struct module *setup_load_info(st @@ -3020,9 +3020,11 @@ static struct module *setup_load_info(st
static int check_modinfo(struct module *mod, struct load_info *info, int flags) static int check_modinfo(struct module *mod, struct load_info *info, int flags)
{ {
@@ -127,7 +127,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (flags & MODULE_INIT_IGNORE_VERMAGIC) if (flags & MODULE_INIT_IGNORE_VERMAGIC)
modmagic = NULL; modmagic = NULL;
@@ -3031,6 +3033,7 @@ static int check_modinfo(struct module * @@ -3043,6 +3045,7 @@ static int check_modinfo(struct module *
mod->name); mod->name);
add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK); add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK);
} }

224
target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch
View File

@@ -830,7 +830,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
--- a/drivers/pci/dwc/pci-dra7xx.c --- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -338,15 +338,6 @@ static irqreturn_t dra7xx_pcie_irq_handl @@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
return IRQ_HANDLED; return IRQ_HANDLED;
} }
@@ -1125,43 +1125,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
struct pci_epf_header *hdr) struct pci_epf_header *hdr)
{ {
struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie_ep *ep = epc_get_drvdata(epc);
@@ -74,8 +106,7 @@ static int dw_pcie_ep_inbound_atu(struct @@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc
u32 free_win;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- free_win = find_first_zero_bit(&ep->ib_window_map,
- sizeof(ep->ib_window_map));
+ free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
if (free_win >= ep->num_ib_windows) {
dev_err(pci->dev, "no free inbound window\n");
return -EINVAL;
@@ -89,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct
}
ep->bar_to_atu[bar] = free_win;
- set_bit(free_win, &ep->ib_window_map);
+ set_bit(free_win, ep->ib_window_map);
return 0;
}
@@ -100,8 +131,7 @@ static int dw_pcie_ep_outbound_atu(struc
u32 free_win;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- free_win = find_first_zero_bit(&ep->ob_window_map,
- sizeof(ep->ob_window_map));
+ free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
if (free_win >= ep->num_ob_windows) {
dev_err(pci->dev, "no free outbound window\n");
return -EINVAL;
@@ -110,30 +140,35 @@ static int dw_pcie_ep_outbound_atu(struc
dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
phys_addr, pci_addr, size);
- set_bit(free_win, &ep->ob_window_map);
+ set_bit(free_win, ep->ob_window_map);
ep->outbound_addr[free_win] = phys_addr;
return 0; return 0;
} }
@@ -1178,8 +1142,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags); + __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
- clear_bit(atu_index, &ep->ib_window_map); clear_bit(atu_index, ep->ib_window_map);
+ clear_bit(atu_index, ep->ib_window_map);
} }
-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar, -static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
@@ -1196,7 +1159,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
enum dw_pcie_as_type as_type; enum dw_pcie_as_type as_type;
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
@@ -142,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci @@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
else else
as_type = DW_PCIE_AS_IO; as_type = DW_PCIE_AS_IO;
@@ -1219,7 +1182,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_dbi_ro_wr_dis(pci);
return 0; return 0;
@@ -169,7 +211,8 @@ static int dw_pcie_find_index(struct dw_ @@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
return -EINVAL; return -EINVAL;
} }
@@ -1229,66 +1192,103 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
{ {
int ret; int ret;
u32 atu_index; u32 atu_index;
@@ -181,10 +224,11 @@ static void dw_pcie_ep_unmap_addr(struct @@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct
return; clear_bit(atu_index, ep->ob_window_map);
dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
- clear_bit(atu_index, &ep->ob_window_map);
+ clear_bit(atu_index, ep->ob_window_map);
} }
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr, -static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
- u64 pci_addr, size_t size)
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, +static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
+ phys_addr_t addr, + phys_addr_t addr,
u64 pci_addr, size_t size) + u64 pci_addr, size_t size)
{ {
int ret; int ret;
@@ -200,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc struct dw_pcie_ep *ep = epc_get_drvdata(epc);
@@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
return 0; return 0;
} }
-static int dw_pcie_ep_get_msi(struct pci_epc *epc) -static int dw_pcie_ep_get_msi(struct pci_epc *epc)
+static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no) +static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
+
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
+ return -EINVAL;
+
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+ return val;
+}
+
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
+
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
+ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_writew_dbi(pci, reg, val);
+ dw_pcie_dbi_ro_wr_dis(pci);
+
+ return 0;
+}
+
+static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
{ {
- int val; - int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg; + u32 val, reg;
+ +
+ if (!ep->msi_cap) + if (!ep->msix_cap)
+ return -EINVAL; + return -EINVAL;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- if (!(val & MSI_CAP_MSI_EN_MASK)) - if (!(val & MSI_CAP_MSI_EN_MASK))
+ reg = ep->msi_cap + PCI_MSI_FLAGS; + reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg); + val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSI_FLAGS_ENABLE)) + if (!(val & PCI_MSIX_FLAGS_ENABLE))
return -EINVAL; return -EINVAL;
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT; - val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; + val &= PCI_MSIX_FLAGS_QSIZE;
+ +
return val; return val;
} }
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) -static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
{ {
- int val; - int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg; + u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- val &= ~MSI_CAP_MMC_MASK; - val &= ~MSI_CAP_MMC_MASK;
- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; - val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+ reg = ep->msi_cap + PCI_MSI_FLAGS; + if (!ep->msix_cap)
+ return -EINVAL;
+
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg); + val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK; + val &= ~PCI_MSIX_FLAGS_QSIZE;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; + val |= interrupts;
dw_pcie_dbi_ro_wr_en(pci); dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); - dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+ dw_pcie_writew_dbi(pci, reg, val); + dw_pcie_writew_dbi(pci, reg, val);
@@ -1299,45 +1299,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc, -static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
- enum pci_epc_irq_type type, u8 interrupt_num) - enum pci_epc_irq_type type, u8 interrupt_num)
+static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msix_cap)
+ return -EINVAL;
+
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSIX_FLAGS_ENABLE))
+ return -EINVAL;
+
+ val &= PCI_MSIX_FLAGS_QSIZE;
+
+ return val;
+}
+
+static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msix_cap)
+ return -EINVAL;
+
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSIX_FLAGS_QSIZE;
+ val |= interrupts;
+ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_writew_dbi(pci, reg, val);
+ dw_pcie_dbi_ro_wr_dis(pci);
+
+ return 0;
+}
+
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, +static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
+ enum pci_epc_irq_type type, u16 interrupt_num) + enum pci_epc_irq_type type, u16 interrupt_num)
{ {
@@ -1351,7 +1312,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
} }
static void dw_pcie_ep_stop(struct pci_epc *epc) static void dw_pcie_ep_stop(struct pci_epc *epc)
@@ -271,15 +363,130 @@ static const struct pci_epc_ops epc_ops @@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops
.unmap_addr = dw_pcie_ep_unmap_addr, .unmap_addr = dw_pcie_ep_unmap_addr,
.set_msi = dw_pcie_ep_set_msi, .set_msi = dw_pcie_ep_set_msi,
.get_msi = dw_pcie_ep_get_msi, .get_msi = dw_pcie_ep_get_msi,
@@ -1482,7 +1443,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
pci_epc_mem_exit(epc); pci_epc_mem_exit(epc);
} }
@@ -293,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e @@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
struct device_node *np = dev->of_node; struct device_node *np = dev->of_node;
if (!pci->dbi_base || !pci->dbi_base2) { if (!pci->dbi_base || !pci->dbi_base2) {
@@ -1491,40 +1452,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
return -EINVAL; return -EINVAL;
} }
@@ -302,12 +509,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e @@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
dev_err(dev, "unable to read *num-ib-windows* property\n");
return ret;
}
+ if (ep->num_ib_windows > MAX_IATU_IN) {
+ dev_err(dev, "invalid *num-ib-windows*\n");
+ return -EINVAL;
+ }
ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
if (ret < 0) {
dev_err(dev, "unable to read *num-ob-windows* property\n");
return ret;
}
+ if (ep->num_ob_windows > MAX_IATU_OUT) {
+ dev_err(dev, "invalid *num-ob-windows*\n");
+ return -EINVAL;
+ }
+
+ ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
+ BITS_TO_LONGS(ep->num_ib_windows),
+ GFP_KERNEL);
+ if (!ep->ib_window_map)
+ return -ENOMEM;
+
+ ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
+ BITS_TO_LONGS(ep->num_ob_windows),
+ GFP_KERNEL);
+ if (!ep->ob_window_map)
+ return -ENOMEM;
addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
GFP_KERNEL);
@@ -315,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
return -ENOMEM; return -ENOMEM;
ep->outbound_addr = addr; ep->outbound_addr = addr;
@@ -1546,7 +1474,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
ret = of_property_read_u8(np, "max-functions", &epc->max_functions); ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
if (ret < 0) if (ret < 0)
epc->max_functions = 1; epc->max_functions = 1;
@@ -335,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e @@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
return ret; return ret;
} }
@@ -1873,9 +1801,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
/* /*
* Maximum number of MSI IRQs can be 256 per controller. But keep * Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed, * it 32 as of now. Probably we will never need more than 32. If needed,
@@ -114,6 +102,10 @@ @@ -118,6 +106,10 @@
#define MAX_MSI_IRQS 32 #define MAX_IATU_IN 256
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) #define MAX_IATU_OUT 256
+/* Maximum number of inbound/outbound iATUs */ +/* Maximum number of inbound/outbound iATUs */
+#define MAX_IATU_IN 256 +#define MAX_IATU_IN 256
@@ -1884,7 +1812,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
struct pcie_port; struct pcie_port;
struct dw_pcie; struct dw_pcie;
struct dw_pcie_ep; struct dw_pcie_ep;
@@ -181,8 +173,8 @@ enum dw_pcie_as_type { @@ -185,8 +177,8 @@ enum dw_pcie_as_type {
struct dw_pcie_ep_ops { struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep); void (*ep_init)(struct dw_pcie_ep *ep);
@@ -1895,14 +1823,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
}; };
struct dw_pcie_ep { struct dw_pcie_ep {
@@ -193,10 +185,14 @@ struct dw_pcie_ep { @@ -201,6 +193,10 @@ struct dw_pcie_ep {
size_t page_size; unsigned long *ob_window_map;
u8 bar_to_atu[6];
phys_addr_t *outbound_addr;
- unsigned long ib_window_map;
- unsigned long ob_window_map;
+ unsigned long *ib_window_map;
+ unsigned long *ob_window_map;
u32 num_ib_windows; u32 num_ib_windows;
u32 num_ob_windows; u32 num_ob_windows;
+ void __iomem *msi_mem; + void __iomem *msi_mem;
@@ -1912,7 +1834,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
}; };
struct dw_pcie_ops { struct dw_pcie_ops {
@@ -335,6 +331,12 @@ static inline int dw_pcie_host_init(stru @@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
@@ -1925,7 +1847,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#else #else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
{ {
@@ -348,5 +350,26 @@ static inline int dw_pcie_ep_init(struct @@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{ {
} }