mediatek: copy patches and files for Linux 6.1
First step only copies patches-5.15 and files-5.15 to patches-6.1 and files-6.1 respectively. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
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* Author: Jianhui Zhao <zhaojh329@gmail.com>
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* Author: Daniel Golle <daniel@makrotopia.org>
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*/
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#ifndef _DT_BINDINGS_CLK_MT7981_H
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#define _DT_BINDINGS_CLK_MT7981_H
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/* TOPCKGEN */
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#define CLK_TOP_CB_CKSQ_40M 0
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#define CLK_TOP_CB_M_416M 1
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#define CLK_TOP_CB_M_D2 2
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#define CLK_TOP_CB_M_D3 3
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#define CLK_TOP_M_D3_D2 4
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#define CLK_TOP_CB_M_D4 5
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#define CLK_TOP_CB_M_D8 6
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#define CLK_TOP_M_D8_D2 7
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#define CLK_TOP_CB_MM_720M 8
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#define CLK_TOP_CB_MM_D2 9
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#define CLK_TOP_CB_MM_D3 10
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#define CLK_TOP_CB_MM_D3_D5 11
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#define CLK_TOP_CB_MM_D4 12
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#define CLK_TOP_CB_MM_D6 13
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#define CLK_TOP_MM_D6_D2 14
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#define CLK_TOP_CB_MM_D8 15
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#define CLK_TOP_CB_APLL2_196M 16
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#define CLK_TOP_APLL2_D2 17
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#define CLK_TOP_APLL2_D4 18
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#define CLK_TOP_NET1_2500M 19
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#define CLK_TOP_CB_NET1_D4 20
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#define CLK_TOP_CB_NET1_D5 21
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#define CLK_TOP_NET1_D5_D2 22
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#define CLK_TOP_NET1_D5_D4 23
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#define CLK_TOP_CB_NET1_D8 24
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#define CLK_TOP_NET1_D8_D2 25
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#define CLK_TOP_NET1_D8_D4 26
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#define CLK_TOP_CB_NET2_800M 27
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#define CLK_TOP_CB_NET2_D2 28
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#define CLK_TOP_CB_NET2_D4 29
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#define CLK_TOP_NET2_D4_D2 30
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#define CLK_TOP_NET2_D4_D4 31
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#define CLK_TOP_CB_NET2_D6 32
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#define CLK_TOP_CB_WEDMCU_208M 33
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#define CLK_TOP_CB_SGM_325M 34
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#define CLK_TOP_CKSQ_40M_D2 35
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#define CLK_TOP_CB_RTC_32K 36
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#define CLK_TOP_CB_RTC_32P7K 37
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#define CLK_TOP_USB_TX250M 38
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#define CLK_TOP_FAUD 39
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#define CLK_TOP_NFI1X 40
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#define CLK_TOP_USB_EQ_RX250M 41
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#define CLK_TOP_USB_CDR_CK 42
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#define CLK_TOP_USB_LN0_CK 43
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#define CLK_TOP_SPINFI_BCK 44
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#define CLK_TOP_SPI 45
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#define CLK_TOP_SPIM_MST 46
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#define CLK_TOP_UART_BCK 47
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#define CLK_TOP_PWM_BCK 48
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#define CLK_TOP_I2C_BCK 49
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#define CLK_TOP_PEXTP_TL 50
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#define CLK_TOP_EMMC_208M 51
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#define CLK_TOP_EMMC_400M 52
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#define CLK_TOP_DRAMC_REF 53
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#define CLK_TOP_DRAMC_MD32 54
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#define CLK_TOP_SYSAXI 55
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#define CLK_TOP_SYSAPB 56
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#define CLK_TOP_ARM_DB_MAIN 57
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#define CLK_TOP_AP2CNN_HOST 58
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#define CLK_TOP_NETSYS 59
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#define CLK_TOP_NETSYS_500M 60
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#define CLK_TOP_NETSYS_WED_MCU 61
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#define CLK_TOP_NETSYS_2X 62
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#define CLK_TOP_SGM_325M 63
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#define CLK_TOP_SGM_REG 64
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#define CLK_TOP_F26M 65
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#define CLK_TOP_EIP97B 66
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#define CLK_TOP_USB3_PHY 67
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#define CLK_TOP_AUD 68
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#define CLK_TOP_A1SYS 69
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#define CLK_TOP_AUD_L 70
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#define CLK_TOP_A_TUNER 71
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#define CLK_TOP_U2U3_REF 72
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#define CLK_TOP_U2U3_SYS 73
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#define CLK_TOP_U2U3_XHCI 74
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#define CLK_TOP_USB_FRMCNT 75
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#define CLK_TOP_NFI1X_SEL 76
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#define CLK_TOP_SPINFI_SEL 77
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#define CLK_TOP_SPI_SEL 78
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#define CLK_TOP_SPIM_MST_SEL 79
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#define CLK_TOP_UART_SEL 80
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#define CLK_TOP_PWM_SEL 81
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#define CLK_TOP_I2C_SEL 82
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#define CLK_TOP_PEXTP_TL_SEL 83
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#define CLK_TOP_EMMC_208M_SEL 84
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#define CLK_TOP_EMMC_400M_SEL 85
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#define CLK_TOP_F26M_SEL 86
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#define CLK_TOP_DRAMC_SEL 87
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#define CLK_TOP_DRAMC_MD32_SEL 88
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#define CLK_TOP_SYSAXI_SEL 89
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#define CLK_TOP_SYSAPB_SEL 90
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#define CLK_TOP_ARM_DB_MAIN_SEL 91
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#define CLK_TOP_AP2CNN_HOST_SEL 92
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#define CLK_TOP_NETSYS_SEL 93
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#define CLK_TOP_NETSYS_500M_SEL 94
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#define CLK_TOP_NETSYS_MCU_SEL 95
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#define CLK_TOP_NETSYS_2X_SEL 96
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#define CLK_TOP_SGM_325M_SEL 97
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#define CLK_TOP_SGM_REG_SEL 98
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#define CLK_TOP_EIP97B_SEL 99
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#define CLK_TOP_USB3_PHY_SEL 100
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#define CLK_TOP_AUD_SEL 101
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#define CLK_TOP_A1SYS_SEL 102
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#define CLK_TOP_AUD_L_SEL 103
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#define CLK_TOP_A_TUNER_SEL 104
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#define CLK_TOP_U2U3_SEL 105
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#define CLK_TOP_U2U3_SYS_SEL 106
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#define CLK_TOP_U2U3_XHCI_SEL 107
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#define CLK_TOP_USB_FRMCNT_SEL 108
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#define CLK_TOP_AUD_I2S_M 109
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/* INFRACFG */
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#define CLK_INFRA_66M_MCK 0
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#define CLK_INFRA_UART0_SEL 1
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#define CLK_INFRA_UART1_SEL 2
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#define CLK_INFRA_UART2_SEL 3
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#define CLK_INFRA_SPI0_SEL 4
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#define CLK_INFRA_SPI1_SEL 5
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#define CLK_INFRA_SPI2_SEL 6
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#define CLK_INFRA_PWM1_SEL 7
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#define CLK_INFRA_PWM2_SEL 8
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#define CLK_INFRA_PWM3_SEL 9
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#define CLK_INFRA_PWM_BSEL 10
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#define CLK_INFRA_PCIE_SEL 11
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#define CLK_INFRA_GPT_STA 12
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#define CLK_INFRA_PWM_HCK 13
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#define CLK_INFRA_PWM_STA 14
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#define CLK_INFRA_PWM1_CK 15
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#define CLK_INFRA_PWM2_CK 16
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#define CLK_INFRA_PWM3_CK 17
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#define CLK_INFRA_CQ_DMA_CK 18
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#define CLK_INFRA_AUD_BUS_CK 19
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#define CLK_INFRA_AUD_26M_CK 20
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#define CLK_INFRA_AUD_L_CK 21
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#define CLK_INFRA_AUD_AUD_CK 22
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#define CLK_INFRA_AUD_EG2_CK 23
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#define CLK_INFRA_DRAMC_26M_CK 24
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#define CLK_INFRA_DBG_CK 25
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#define CLK_INFRA_AP_DMA_CK 26
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#define CLK_INFRA_SEJ_CK 27
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#define CLK_INFRA_SEJ_13M_CK 28
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#define CLK_INFRA_THERM_CK 29
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#define CLK_INFRA_I2C0_CK 30
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#define CLK_INFRA_UART0_CK 31
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#define CLK_INFRA_UART1_CK 32
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#define CLK_INFRA_UART2_CK 33
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#define CLK_INFRA_SPI2_CK 34
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#define CLK_INFRA_SPI2_HCK_CK 35
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#define CLK_INFRA_NFI1_CK 36
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#define CLK_INFRA_SPINFI1_CK 37
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#define CLK_INFRA_NFI_HCK_CK 38
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#define CLK_INFRA_SPI0_CK 39
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#define CLK_INFRA_SPI1_CK 40
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#define CLK_INFRA_SPI0_HCK_CK 41
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#define CLK_INFRA_SPI1_HCK_CK 42
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#define CLK_INFRA_FRTC_CK 43
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#define CLK_INFRA_MSDC_CK 44
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#define CLK_INFRA_MSDC_HCK_CK 45
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#define CLK_INFRA_MSDC_133M_CK 46
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#define CLK_INFRA_MSDC_66M_CK 47
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#define CLK_INFRA_ADC_26M_CK 48
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#define CLK_INFRA_ADC_FRC_CK 49
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#define CLK_INFRA_FBIST2FPC_CK 50
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#define CLK_INFRA_I2C_MCK_CK 51
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#define CLK_INFRA_I2C_PCK_CK 52
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#define CLK_INFRA_IUSB_133_CK 53
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#define CLK_INFRA_IUSB_66M_CK 54
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#define CLK_INFRA_IUSB_SYS_CK 55
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#define CLK_INFRA_IUSB_CK 56
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#define CLK_INFRA_IPCIE_CK 57
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#define CLK_INFRA_IPCIE_PIPE_CK 58
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#define CLK_INFRA_IPCIER_CK 59
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#define CLK_INFRA_IPCIEB_CK 60
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_NET2PLL 1
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#define CLK_APMIXED_MMPLL 2
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#define CLK_APMIXED_SGMPLL 3
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#define CLK_APMIXED_WEDMCUPLL 4
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#define CLK_APMIXED_NET1PLL 5
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#define CLK_APMIXED_MPLL 6
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#define CLK_APMIXED_APLL2 7
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/* SGMIISYS_0 */
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#define CLK_SGM0_TX_EN 0
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#define CLK_SGM0_RX_EN 1
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#define CLK_SGM0_CK0_EN 2
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#define CLK_SGM0_CDR_CK0_EN 3
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/* SGMIISYS_1 */
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#define CLK_SGM1_TX_EN 0
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#define CLK_SGM1_RX_EN 1
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#define CLK_SGM1_CK1_EN 2
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#define CLK_SGM1_CDR_CK1_EN 3
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/* ETHSYS */
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#define CLK_ETH_FE_EN 0
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#define CLK_ETH_GP2_EN 1
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#define CLK_ETH_GP1_EN 2
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#define CLK_ETH_WOCPU0_EN 3
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#endif /* _DT_BINDINGS_CLK_MT7981_H */
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@@ -0,0 +1,276 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT7988_H
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#define _DT_BINDINGS_CLK_MT7988_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_NETSYSPLL 0
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#define CLK_APMIXED_MPLL 1
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#define CLK_APMIXED_MMPLL 2
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#define CLK_APMIXED_APLL2 3
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#define CLK_APMIXED_NET1PLL 4
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#define CLK_APMIXED_NET2PLL 5
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#define CLK_APMIXED_WEDMCUPLL 6
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#define CLK_APMIXED_SGMPLL 7
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#define CLK_APMIXED_ARM_B 8
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#define CLK_APMIXED_CCIPLL2_B 9
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#define CLK_APMIXED_USXGMIIPLL 10
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#define CLK_APMIXED_MSDCPLL 11
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/* TOPCKGEN */
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#define CLK_TOP_XTAL 0
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#define CLK_TOP_XTAL_D2 1
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#define CLK_TOP_RTC_32K 2
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#define CLK_TOP_RTC_32P7K 3
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#define CLK_TOP_MPLL_D2 4
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#define CLK_TOP_MPLL_D3_D2 5
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#define CLK_TOP_MPLL_D4 6
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#define CLK_TOP_MPLL_D8 7
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#define CLK_TOP_MPLL_D8_D2 8
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#define CLK_TOP_MMPLL_D2 9
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#define CLK_TOP_MMPLL_D3_D5 10
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#define CLK_TOP_MMPLL_D4 11
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#define CLK_TOP_MMPLL_D6_D2 12
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#define CLK_TOP_MMPLL_D8 13
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#define CLK_TOP_APLL2_D4 14
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#define CLK_TOP_NET1PLL_D4 15
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#define CLK_TOP_NET1PLL_D5 16
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#define CLK_TOP_NET1PLL_D5_D2 17
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#define CLK_TOP_NET1PLL_D5_D4 18
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#define CLK_TOP_NET1PLL_D8 19
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#define CLK_TOP_NET1PLL_D8_D2 20
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#define CLK_TOP_NET1PLL_D8_D4 21
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#define CLK_TOP_NET1PLL_D8_D8 22
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#define CLK_TOP_NET1PLL_D8_D16 23
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#define CLK_TOP_NET2PLL_D2 24
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#define CLK_TOP_NET2PLL_D4 25
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#define CLK_TOP_NET2PLL_D4_D4 26
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#define CLK_TOP_NET2PLL_D4_D8 27
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#define CLK_TOP_NET2PLL_D6 28
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#define CLK_TOP_NET2PLL_D8 29
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#define CLK_TOP_NETSYS_SEL 30
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#define CLK_TOP_NETSYS_500M_SEL 31
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#define CLK_TOP_NETSYS_2X_SEL 32
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#define CLK_TOP_NETSYS_GSW_SEL 33
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#define CLK_TOP_ETH_GMII_SEL 34
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#define CLK_TOP_NETSYS_MCU_SEL 35
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#define CLK_TOP_NETSYS_PAO_2X_SEL 36
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#define CLK_TOP_EIP197_SEL 37
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#define CLK_TOP_AXI_INFRA_SEL 38
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#define CLK_TOP_UART_SEL 39
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#define CLK_TOP_EMMC_250M_SEL 40
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#define CLK_TOP_EMMC_400M_SEL 41
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#define CLK_TOP_SPI_SEL 42
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#define CLK_TOP_SPIM_MST_SEL 43
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#define CLK_TOP_NFI1X_SEL 44
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#define CLK_TOP_SPINFI_SEL 45
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#define CLK_TOP_PWM_SEL 46
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#define CLK_TOP_I2C_SEL 47
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#define CLK_TOP_PCIE_MBIST_250M_SEL 48
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#define CLK_TOP_PEXTP_TL_SEL 49
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#define CLK_TOP_PEXTP_TL_P1_SEL 50
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#define CLK_TOP_PEXTP_TL_P2_SEL 51
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#define CLK_TOP_PEXTP_TL_P3_SEL 52
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#define CLK_TOP_USB_SYS_SEL 53
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#define CLK_TOP_USB_SYS_P1_SEL 54
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#define CLK_TOP_USB_XHCI_SEL 55
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#define CLK_TOP_USB_XHCI_P1_SEL 56
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#define CLK_TOP_USB_FRMCNT_SEL 57
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#define CLK_TOP_USB_FRMCNT_P1_SEL 58
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#define CLK_TOP_AUD_SEL 59
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#define CLK_TOP_A1SYS_SEL 60
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#define CLK_TOP_AUD_L_SEL 61
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#define CLK_TOP_A_TUNER_SEL 62
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#define CLK_TOP_SSPXTP_SEL 63
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#define CLK_TOP_USB_PHY_SEL 64
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#define CLK_TOP_USXGMII_SBUS_0_SEL 65
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#define CLK_TOP_USXGMII_SBUS_1_SEL 66
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#define CLK_TOP_SGM_0_SEL 67
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#define CLK_TOP_SGM_SBUS_0_SEL 68
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#define CLK_TOP_SGM_1_SEL 69
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#define CLK_TOP_SGM_SBUS_1_SEL 70
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#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
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#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
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#define CLK_TOP_SYSAXI_SEL 73
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#define CLK_TOP_SYSAPB_SEL 74
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#define CLK_TOP_ETH_REFCK_50M_SEL 75
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#define CLK_TOP_ETH_SYS_200M_SEL 76
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#define CLK_TOP_ETH_SYS_SEL 77
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#define CLK_TOP_ETH_XGMII_SEL 78
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#define CLK_TOP_BUS_TOPS_SEL 79
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#define CLK_TOP_NPU_TOPS_SEL 80
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#define CLK_TOP_DRAMC_SEL 81
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#define CLK_TOP_DRAMC_MD32_SEL 82
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#define CLK_TOP_INFRA_F26M_SEL 83
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#define CLK_TOP_PEXTP_P0_SEL 84
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#define CLK_TOP_PEXTP_P1_SEL 85
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#define CLK_TOP_PEXTP_P2_SEL 86
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#define CLK_TOP_PEXTP_P3_SEL 87
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#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
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#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
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#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
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#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
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#define CLK_TOP_CKM_SEL 92
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#define CLK_TOP_DA_SEL 93
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#define CLK_TOP_PEXTP_SEL 94
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#define CLK_TOP_TOPS_P2_26M_SEL 95
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#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
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#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
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#define CLK_TOP_MACSEC_SEL 98
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#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
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#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
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#define CLK_TOP_NETSYS_WARP_SEL 101
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#define CLK_TOP_ETH_MII_SEL 102
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#define CLK_TOP_NPU_SEL 103
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#define CLK_TOP_AUD_I2S_M 104
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/* MCUSYS */
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#define CLK_MCU_BUS_DIV_SEL 0
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#define CLK_MCU_ARM_DIV_SEL 1
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/* INFRACFG_AO */
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#define CLK_INFRA_MUX_UART0_SEL 0
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#define CLK_INFRA_MUX_UART1_SEL 1
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#define CLK_INFRA_MUX_UART2_SEL 2
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#define CLK_INFRA_MUX_SPI0_SEL 3
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#define CLK_INFRA_MUX_SPI1_SEL 4
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#define CLK_INFRA_MUX_SPI2_SEL 5
|
||||
#define CLK_INFRA_PWM_SEL 6
|
||||
#define CLK_INFRA_PWM_CK1_SEL 7
|
||||
#define CLK_INFRA_PWM_CK2_SEL 8
|
||||
#define CLK_INFRA_PWM_CK3_SEL 9
|
||||
#define CLK_INFRA_PWM_CK4_SEL 10
|
||||
#define CLK_INFRA_PWM_CK5_SEL 11
|
||||
#define CLK_INFRA_PWM_CK6_SEL 12
|
||||
#define CLK_INFRA_PWM_CK7_SEL 13
|
||||
#define CLK_INFRA_PWM_CK8_SEL 14
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
|
||||
#define CLK_INFRA_66M_GPT_BCK 23
|
||||
#define CLK_INFRA_66M_PWM_HCK 24
|
||||
#define CLK_INFRA_66M_PWM_BCK 25
|
||||
#define CLK_INFRA_66M_PWM_CK1 26
|
||||
#define CLK_INFRA_66M_PWM_CK2 27
|
||||
#define CLK_INFRA_66M_PWM_CK3 28
|
||||
#define CLK_INFRA_66M_PWM_CK4 29
|
||||
#define CLK_INFRA_66M_PWM_CK5 30
|
||||
#define CLK_INFRA_66M_PWM_CK6 31
|
||||
#define CLK_INFRA_66M_PWM_CK7 32
|
||||
#define CLK_INFRA_66M_PWM_CK8 33
|
||||
#define CLK_INFRA_133M_CQDMA_BCK 34
|
||||
#define CLK_INFRA_66M_AUD_SLV_BCK 35
|
||||
#define CLK_INFRA_AUD_26M 36
|
||||
#define CLK_INFRA_AUD_L 37
|
||||
#define CLK_INFRA_AUD_AUD 38
|
||||
#define CLK_INFRA_AUD_EG2 39
|
||||
#define CLK_INFRA_DRAMC_F26M 40
|
||||
#define CLK_INFRA_133M_DBG_ACKM 41
|
||||
#define CLK_INFRA_66M_AP_DMA_BCK 42
|
||||
#define CLK_INFRA_66M_SEJ_BCK 43
|
||||
#define CLK_INFRA_PRE_CK_SEJ_F13M 44
|
||||
#define CLK_INFRA_26M_THERM_SYSTEM 45
|
||||
#define CLK_INFRA_I2C_BCK 46
|
||||
#define CLK_INFRA_52M_UART0_CK 47
|
||||
#define CLK_INFRA_52M_UART1_CK 48
|
||||
#define CLK_INFRA_52M_UART2_CK 49
|
||||
#define CLK_INFRA_NFI 50
|
||||
#define CLK_INFRA_SPINFI 51
|
||||
#define CLK_INFRA_66M_NFI_HCK 52
|
||||
#define CLK_INFRA_104M_SPI0 53
|
||||
#define CLK_INFRA_104M_SPI1 54
|
||||
#define CLK_INFRA_104M_SPI2_BCK 55
|
||||
#define CLK_INFRA_66M_SPI0_HCK 56
|
||||
#define CLK_INFRA_66M_SPI1_HCK 57
|
||||
#define CLK_INFRA_66M_SPI2_HCK 58
|
||||
#define CLK_INFRA_66M_FLASHIF_AXI 59
|
||||
#define CLK_INFRA_RTC 60
|
||||
#define CLK_INFRA_26M_ADC_BCK 61
|
||||
#define CLK_INFRA_RC_ADC 62
|
||||
#define CLK_INFRA_MSDC400 63
|
||||
#define CLK_INFRA_MSDC2_HCK 64
|
||||
#define CLK_INFRA_133M_MSDC_0_HCK 65
|
||||
#define CLK_INFRA_66M_MSDC_0_HCK 66
|
||||
#define CLK_INFRA_133M_CPUM_BCK 67
|
||||
#define CLK_INFRA_BIST2FPC 68
|
||||
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
|
||||
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
|
||||
#define CLK_INFRA_133M_USB_HCK 71
|
||||
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
|
||||
#define CLK_INFRA_66M_USB_HCK 73
|
||||
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
|
||||
#define CLK_INFRA_USB_SYS 75
|
||||
#define CLK_INFRA_USB_SYS_CK_P1 76
|
||||
#define CLK_INFRA_USB_REF 77
|
||||
#define CLK_INFRA_USB_CK_P1 78
|
||||
#define CLK_INFRA_USB_FRMCNT 79
|
||||
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
|
||||
#define CLK_INFRA_USB_PIPE 81
|
||||
#define CLK_INFRA_USB_PIPE_CK_P1 82
|
||||
#define CLK_INFRA_USB_UTMI 83
|
||||
#define CLK_INFRA_USB_UTMI_CK_P1 84
|
||||
#define CLK_INFRA_USB_XHCI 85
|
||||
#define CLK_INFRA_USB_XHCI_CK_P1 86
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
|
||||
#define CLK_INFRA_PCIE_PIPE_P0 91
|
||||
#define CLK_INFRA_PCIE_PIPE_P1 92
|
||||
#define CLK_INFRA_PCIE_PIPE_P2 93
|
||||
#define CLK_INFRA_PCIE_PIPE_P3 94
|
||||
#define CLK_INFRA_133M_PCIE_CK_P0 95
|
||||
#define CLK_INFRA_133M_PCIE_CK_P1 96
|
||||
#define CLK_INFRA_133M_PCIE_CK_P2 97
|
||||
#define CLK_INFRA_133M_PCIE_CK_P3 98
|
||||
|
||||
/* ETHDMA */
|
||||
|
||||
#define CLK_ETHDMA_XGP1_EN 0
|
||||
#define CLK_ETHDMA_XGP2_EN 1
|
||||
#define CLK_ETHDMA_XGP3_EN 2
|
||||
#define CLK_ETHDMA_FE_EN 3
|
||||
#define CLK_ETHDMA_GP2_EN 4
|
||||
#define CLK_ETHDMA_GP1_EN 5
|
||||
#define CLK_ETHDMA_GP3_EN 6
|
||||
#define CLK_ETHDMA_ESW_EN 7
|
||||
#define CLK_ETHDMA_CRYPT0_EN 8
|
||||
#define CLK_ETHDMA_NR_CLK 9
|
||||
|
||||
/* SGMIISYS_0 */
|
||||
|
||||
#define CLK_SGM0_TX_EN 0
|
||||
#define CLK_SGM0_RX_EN 1
|
||||
#define CLK_SGMII0_NR_CLK 2
|
||||
|
||||
/* SGMIISYS_1 */
|
||||
|
||||
#define CLK_SGM1_TX_EN 0
|
||||
#define CLK_SGM1_RX_EN 1
|
||||
#define CLK_SGMII1_NR_CLK 2
|
||||
|
||||
/* ETHWARP */
|
||||
|
||||
#define CLK_ETHWARP_WOCPU2_EN 0
|
||||
#define CLK_ETHWARP_WOCPU1_EN 1
|
||||
#define CLK_ETHWARP_WOCPU0_EN 2
|
||||
#define CLK_ETHWARP_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7988_H */
|
||||
@@ -0,0 +1,169 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT7986_H
|
||||
#define _DT_BINDINGS_CLK_MT7986_H
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_ARMPLL 0
|
||||
#define CLK_APMIXED_NET2PLL 1
|
||||
#define CLK_APMIXED_MMPLL 2
|
||||
#define CLK_APMIXED_SGMPLL 3
|
||||
#define CLK_APMIXED_WEDMCUPLL 4
|
||||
#define CLK_APMIXED_NET1PLL 5
|
||||
#define CLK_APMIXED_MPLL 6
|
||||
#define CLK_APMIXED_APLL2 7
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_XTAL 0
|
||||
#define CLK_TOP_XTAL_D2 1
|
||||
#define CLK_TOP_RTC_32K 2
|
||||
#define CLK_TOP_RTC_32P7K 3
|
||||
#define CLK_TOP_MPLL_D2 4
|
||||
#define CLK_TOP_MPLL_D4 5
|
||||
#define CLK_TOP_MPLL_D8 6
|
||||
#define CLK_TOP_MPLL_D8_D2 7
|
||||
#define CLK_TOP_MPLL_D3_D2 8
|
||||
#define CLK_TOP_MMPLL_D2 9
|
||||
#define CLK_TOP_MMPLL_D4 10
|
||||
#define CLK_TOP_MMPLL_D8 11
|
||||
#define CLK_TOP_MMPLL_D8_D2 12
|
||||
#define CLK_TOP_MMPLL_D3_D8 13
|
||||
#define CLK_TOP_MMPLL_U2PHY 14
|
||||
#define CLK_TOP_APLL2_D4 15
|
||||
#define CLK_TOP_NET1PLL_D4 16
|
||||
#define CLK_TOP_NET1PLL_D5 17
|
||||
#define CLK_TOP_NET1PLL_D5_D2 18
|
||||
#define CLK_TOP_NET1PLL_D5_D4 19
|
||||
#define CLK_TOP_NET1PLL_D8_D2 20
|
||||
#define CLK_TOP_NET1PLL_D8_D4 21
|
||||
#define CLK_TOP_NET2PLL_D4 22
|
||||
#define CLK_TOP_NET2PLL_D4_D2 23
|
||||
#define CLK_TOP_NET2PLL_D3_D2 24
|
||||
#define CLK_TOP_WEDMCUPLL_D5_D2 25
|
||||
#define CLK_TOP_NFI1X_SEL 26
|
||||
#define CLK_TOP_SPINFI_SEL 27
|
||||
#define CLK_TOP_SPI_SEL 28
|
||||
#define CLK_TOP_SPIM_MST_SEL 29
|
||||
#define CLK_TOP_UART_SEL 30
|
||||
#define CLK_TOP_PWM_SEL 31
|
||||
#define CLK_TOP_I2C_SEL 32
|
||||
#define CLK_TOP_PEXTP_TL_SEL 33
|
||||
#define CLK_TOP_EMMC_250M_SEL 34
|
||||
#define CLK_TOP_EMMC_416M_SEL 35
|
||||
#define CLK_TOP_F_26M_ADC_SEL 36
|
||||
#define CLK_TOP_DRAMC_SEL 37
|
||||
#define CLK_TOP_DRAMC_MD32_SEL 38
|
||||
#define CLK_TOP_SYSAXI_SEL 39
|
||||
#define CLK_TOP_SYSAPB_SEL 40
|
||||
#define CLK_TOP_ARM_DB_MAIN_SEL 41
|
||||
#define CLK_TOP_ARM_DB_JTSEL 42
|
||||
#define CLK_TOP_NETSYS_SEL 43
|
||||
#define CLK_TOP_NETSYS_500M_SEL 44
|
||||
#define CLK_TOP_NETSYS_MCU_SEL 45
|
||||
#define CLK_TOP_NETSYS_2X_SEL 46
|
||||
#define CLK_TOP_SGM_325M_SEL 47
|
||||
#define CLK_TOP_SGM_REG_SEL 48
|
||||
#define CLK_TOP_A1SYS_SEL 49
|
||||
#define CLK_TOP_CONN_MCUSYS_SEL 50
|
||||
#define CLK_TOP_EIP_B_SEL 51
|
||||
#define CLK_TOP_PCIE_PHY_SEL 52
|
||||
#define CLK_TOP_USB3_PHY_SEL 53
|
||||
#define CLK_TOP_F26M_SEL 54
|
||||
#define CLK_TOP_AUD_L_SEL 55
|
||||
#define CLK_TOP_A_TUNER_SEL 56
|
||||
#define CLK_TOP_U2U3_SEL 57
|
||||
#define CLK_TOP_U2U3_SYS_SEL 58
|
||||
#define CLK_TOP_U2U3_XHCI_SEL 59
|
||||
#define CLK_TOP_DA_U2_REFSEL 60
|
||||
#define CLK_TOP_DA_U2_CK_1P_SEL 61
|
||||
#define CLK_TOP_AP2CNN_HOST_SEL 62
|
||||
#define CLK_TOP_JTAG 63
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_INFRA_SYSAXI_D2 0
|
||||
#define CLK_INFRA_UART0_SEL 1
|
||||
#define CLK_INFRA_UART1_SEL 2
|
||||
#define CLK_INFRA_UART2_SEL 3
|
||||
#define CLK_INFRA_SPI0_SEL 4
|
||||
#define CLK_INFRA_SPI1_SEL 5
|
||||
#define CLK_INFRA_PWM1_SEL 6
|
||||
#define CLK_INFRA_PWM2_SEL 7
|
||||
#define CLK_INFRA_PWM_BSEL 8
|
||||
#define CLK_INFRA_PCIE_SEL 9
|
||||
#define CLK_INFRA_GPT_STA 10
|
||||
#define CLK_INFRA_PWM_HCK 11
|
||||
#define CLK_INFRA_PWM_STA 12
|
||||
#define CLK_INFRA_PWM1_CK 13
|
||||
#define CLK_INFRA_PWM2_CK 14
|
||||
#define CLK_INFRA_CQ_DMA_CK 15
|
||||
#define CLK_INFRA_EIP97_CK 16
|
||||
#define CLK_INFRA_AUD_BUS_CK 17
|
||||
#define CLK_INFRA_AUD_26M_CK 18
|
||||
#define CLK_INFRA_AUD_L_CK 19
|
||||
#define CLK_INFRA_AUD_AUD_CK 20
|
||||
#define CLK_INFRA_AUD_EG2_CK 21
|
||||
#define CLK_INFRA_DRAMC_26M_CK 22
|
||||
#define CLK_INFRA_DBG_CK 23
|
||||
#define CLK_INFRA_AP_DMA_CK 24
|
||||
#define CLK_INFRA_SEJ_CK 25
|
||||
#define CLK_INFRA_SEJ_13M_CK 26
|
||||
#define CLK_INFRA_THERM_CK 27
|
||||
#define CLK_INFRA_I2C0_CK 28
|
||||
#define CLK_INFRA_UART0_CK 29
|
||||
#define CLK_INFRA_UART1_CK 30
|
||||
#define CLK_INFRA_UART2_CK 31
|
||||
#define CLK_INFRA_NFI1_CK 32
|
||||
#define CLK_INFRA_SPINFI1_CK 33
|
||||
#define CLK_INFRA_NFI_HCK_CK 34
|
||||
#define CLK_INFRA_SPI0_CK 35
|
||||
#define CLK_INFRA_SPI1_CK 36
|
||||
#define CLK_INFRA_SPI0_HCK_CK 37
|
||||
#define CLK_INFRA_SPI1_HCK_CK 38
|
||||
#define CLK_INFRA_FRTC_CK 39
|
||||
#define CLK_INFRA_MSDC_CK 40
|
||||
#define CLK_INFRA_MSDC_HCK_CK 41
|
||||
#define CLK_INFRA_MSDC_133M_CK 42
|
||||
#define CLK_INFRA_MSDC_66M_CK 43
|
||||
#define CLK_INFRA_ADC_26M_CK 44
|
||||
#define CLK_INFRA_ADC_FRC_CK 45
|
||||
#define CLK_INFRA_FBIST2FPC_CK 46
|
||||
#define CLK_INFRA_IUSB_133_CK 47
|
||||
#define CLK_INFRA_IUSB_66M_CK 48
|
||||
#define CLK_INFRA_IUSB_SYS_CK 49
|
||||
#define CLK_INFRA_IUSB_CK 50
|
||||
#define CLK_INFRA_IPCIE_CK 51
|
||||
#define CLK_INFRA_IPCIE_PIPE_CK 52
|
||||
#define CLK_INFRA_IPCIER_CK 53
|
||||
#define CLK_INFRA_IPCIEB_CK 54
|
||||
#define CLK_INFRA_TRNG_CK 55
|
||||
|
||||
/* SGMIISYS_0 */
|
||||
|
||||
#define CLK_SGMII0_TX250M_EN 0
|
||||
#define CLK_SGMII0_RX250M_EN 1
|
||||
#define CLK_SGMII0_CDR_REF 2
|
||||
#define CLK_SGMII0_CDR_FB 3
|
||||
|
||||
/* SGMIISYS_1 */
|
||||
|
||||
#define CLK_SGMII1_TX250M_EN 0
|
||||
#define CLK_SGMII1_RX250M_EN 1
|
||||
#define CLK_SGMII1_CDR_REF 2
|
||||
#define CLK_SGMII1_CDR_FB 3
|
||||
|
||||
/* ETHSYS */
|
||||
|
||||
#define CLK_ETH_FE_EN 0
|
||||
#define CLK_ETH_GP2_EN 1
|
||||
#define CLK_ETH_GP1_EN 2
|
||||
#define CLK_ETH_WOCPU1_EN 3
|
||||
#define CLK_ETH_WOCPU0_EN 4
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7986_H */
|
||||
@@ -0,0 +1,55 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
|
||||
|
||||
/* INFRACFG resets */
|
||||
#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
|
||||
#define MT7986_INFRACFG_SSUSB_SW_RST 7
|
||||
#define MT7986_INFRACFG_EIP97_SW_RST 8
|
||||
#define MT7986_INFRACFG_AUDIO_SW_RST 13
|
||||
#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
|
||||
|
||||
#define MT7986_INFRACFG_TRNG_SW_RST 17
|
||||
#define MT7986_INFRACFG_AP_DMA_SW_RST 32
|
||||
#define MT7986_INFRACFG_I2C_SW_RST 33
|
||||
#define MT7986_INFRACFG_NFI_SW_RST 34
|
||||
#define MT7986_INFRACFG_SPI0_SW_RST 35
|
||||
#define MT7986_INFRACFG_SPI1_SW_RST 36
|
||||
#define MT7986_INFRACFG_UART0_SW_RST 37
|
||||
#define MT7986_INFRACFG_UART1_SW_RST 38
|
||||
#define MT7986_INFRACFG_UART2_SW_RST 39
|
||||
#define MT7986_INFRACFG_AUXADC_SW_RST 43
|
||||
|
||||
#define MT7986_INFRACFG_APXGPT_SW_RST 66
|
||||
#define MT7986_INFRACFG_PWM_SW_RST 68
|
||||
|
||||
#define MT7986_INFRACFG_SW_RST_NUM 69
|
||||
|
||||
/* TOPRGU resets */
|
||||
#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
|
||||
#define MT7986_TOPRGU_SGMII0_SW_RST 1
|
||||
#define MT7986_TOPRGU_SGMII1_SW_RST 2
|
||||
#define MT7986_TOPRGU_INFRA_SW_RST 3
|
||||
#define MT7986_TOPRGU_U2PHY_SW_RST 5
|
||||
#define MT7986_TOPRGU_PCIE_SW_RST 6
|
||||
#define MT7986_TOPRGU_SSUSB_SW_RST 7
|
||||
#define MT7986_TOPRGU_ETHDMA_SW_RST 20
|
||||
#define MT7986_TOPRGU_CONSYS_SW_RST 23
|
||||
|
||||
#define MT7986_TOPRGU_SW_RST_NUM 24
|
||||
|
||||
/* ETHSYS Subsystem resets */
|
||||
#define MT7986_ETHSYS_FE_SW_RST 6
|
||||
#define MT7986_ETHSYS_PMTR_SW_RST 8
|
||||
#define MT7986_ETHSYS_GMAC_SW_RST 23
|
||||
#define MT7986_ETHSYS_PPE0_SW_RST 30
|
||||
#define MT7986_ETHSYS_PPE1_SW_RST 31
|
||||
|
||||
#define MT7986_ETHSYS_SW_RST_NUM 32
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
|
||||
Reference in New Issue
Block a user