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ramips: minor tweak to the lks7688 baord name

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Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 47388
This commit is contained in:
John Crispin
2015-11-05 10:01:23 +00:00
parent a2a7aba257
commit dc699dd547
4 changed files with 24 additions and 68 deletions
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44
target/linux/ramips/patches-3.18/0300-mt7628_fixes.patch
View File

@@ -1,49 +1,5 @@
--- a/arch/mips/ralink/mt7620.c --- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c
@@ -101,28 +101,28 @@ static struct rt2880_pmx_group mt7620a_p
};
static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
- FUNC("sdxc", 3, 19, 1),
+ FUNC("sdxc d6", 3, 19, 1),
FUNC("utif", 2, 19, 1),
FUNC("gpio", 1, 19, 1),
- FUNC("pwm", 0, 19, 1),
+ FUNC("pwm1", 0, 19, 1),
};
static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
- FUNC("sdxc", 3, 18, 1),
+ FUNC("sdxc d7", 3, 18, 1),
FUNC("utif", 2, 18, 1),
FUNC("gpio", 1, 18, 1),
- FUNC("pwm", 0, 18, 1),
+ FUNC("pwm0", 0, 18, 1),
};
static struct rt2880_pmx_func uart2_grp_mt7628[] = {
- FUNC("sdxc", 3, 20, 2),
+ FUNC("sdxc d5 d4", 3, 20, 2),
FUNC("pwm", 2, 20, 2),
FUNC("gpio", 1, 20, 2),
FUNC("uart2", 0, 20, 2),
};
static struct rt2880_pmx_func uart1_grp_mt7628[] = {
- FUNC("sdxc", 3, 45, 2),
+ FUNC("sw_r", 3, 45, 2),
FUNC("pwm", 2, 45, 2),
FUNC("gpio", 1, 45, 2),
FUNC("uart1", 0, 45, 2),
@@ -165,7 +165,7 @@ static struct rt2880_pmx_func spi_cs1_gr
FUNC("-", 3, 6, 1),
FUNC("refclk", 2, 6, 1),
FUNC("gpio", 1, 6, 1),
- FUNC("spi", 0, 6, 1),
+ FUNC("spi cs1", 0, 6, 1),
};
static struct rt2880_pmx_func spis_grp_mt7628[] = {
@@ -182,27 +182,43 @@ static struct rt2880_pmx_func gpio_grp_m @@ -182,27 +182,43 @@ static struct rt2880_pmx_func gpio_grp_m
FUNC("gpio", 0, 11, 1), FUNC("gpio", 0, 11, 1),
}; };

44
target/linux/ramips/patches-3.18/0301-mt7688-detect.patch
View File

@@ -24,8 +24,8 @@
#define RINT(x) ((x) / 1000000) #define RINT(x) ((x) / 1000000)
#define RFRAC(x) (((x) / 1000) % 1000) #define RFRAC(x) (((x) / 1000) % 1000)
- if (ralink_soc == MT762X_SOC_MT7628AN) { - if (mt762x_soc == MT762X_SOC_MT7628AN) {
+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { + if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
if (xtal_rate == MHZ(40)) if (xtal_rate == MHZ(40))
cpu_rate = MHZ(580); cpu_rate = MHZ(580);
else else
@@ -33,64 +33,64 @@
ralink_clk_add("10000e00.uart2", periph_rate); ralink_clk_add("10000e00.uart2", periph_rate);
ralink_clk_add("10180000.wmac", xtal_rate); ralink_clk_add("10180000.wmac", xtal_rate);
- if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) { - if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
+ if (IS_ENABLED(CONFIG_USB) && + if (IS_ENABLED(CONFIG_USB) &&
+ (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) { + (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
/* /*
* When the CPU goes into sleep mode, the BUS clock will be too low for * When the CPU goes into sleep mode, the BUS clock will be too low for
* USB to function properly * USB to function properly
@@ -533,8 +537,15 @@ void prom_soc_init(struct ralink_soc_inf @@ -533,8 +537,15 @@ void prom_soc_init(struct mt762x_soc_inf
soc_info->compatible = "ralink,mt7620n-soc"; soc_info->compatible = "ralink,mt7620n-soc";
} }
} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
- ralink_soc = MT762X_SOC_MT7628AN; - mt762x_soc = MT762X_SOC_MT7628AN;
- name = "MT7628AN"; - name = "MT7628AN";
+ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); + u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
+ +
+ if (efuse & EFUSE_MT7688) { + if (efuse & EFUSE_MT7688) {
+ ralink_soc = MT762X_SOC_MT7688; + mt762x_soc = MT762X_SOC_MT7688;
+ name = "MT7688"; + name = "MT7688";
+ } else { + } else {
+ ralink_soc = MT762X_SOC_MT7628AN; + mt762x_soc = MT762X_SOC_MT7628AN;
+ name = "MT7628AN"; + name = "MT7628AN";
+ } + }
soc_info->compatible = "ralink,mt7628an-soc"; soc_info->compatible = "ralink,mt7628an-soc";
} else { } else {
panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
@@ -548,13 +559,13 @@ void prom_soc_init(struct ralink_soc_inf @@ -548,13 +559,13 @@ void prom_soc_init(struct mt762x_soc_inf
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
- if (ralink_soc == MT762X_SOC_MT7628AN) - if (mt762x_soc == MT762X_SOC_MT7628AN)
+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) + if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628; dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628;
else else
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
soc_info->mem_base = MT7620_DRAM_BASE; soc_info->mem_base = MT7620_DRAM_BASE;
- if (ralink_soc == MT762X_SOC_MT7628AN) - if (mt762x_soc == MT762X_SOC_MT7628AN)
+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) + if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
mt7628_dram_init(soc_info); mt7628_dram_init(soc_info);
else else
mt7620_dram_init(soc_info); mt7620_dram_init(soc_info);
@@ -567,7 +578,7 @@ void prom_soc_init(struct ralink_soc_inf @@ -567,7 +578,7 @@ void prom_soc_init(struct mt762x_soc_inf
pr_info("Digital PMU set to %s control\n", pr_info("Digital PMU set to %s control\n",
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
- if (ralink_soc == MT762X_SOC_MT7628AN) - if (mt762x_soc == MT762X_SOC_MT7628AN)
+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) + if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
rt2880_pinmux_data = mt7628an_pinmux_data; rt2880_pinmux_data = mt7628an_pinmux_data;
else else
rt2880_pinmux_data = mt7620a_pinmux_data; rt2880_pinmux_data = mt7620a_pinmux_data;
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -24,6 +24,7 @@ enum ralink_soc_type { @@ -24,6 +24,7 @@ enum mt762x_soc_type {
MT762X_SOC_MT7620N, MT762X_SOC_MT7620N,
MT762X_SOC_MT7621AT, MT762X_SOC_MT7621AT,
MT762X_SOC_MT7628AN, MT762X_SOC_MT7628AN,
+ MT762X_SOC_MT7688, + MT762X_SOC_MT7688,
}; };
extern enum ralink_soc_type ralink_soc; extern enum mt762x_soc_type mt762x_soc;
--- a/drivers/net/ethernet/ralink/esw_rt3052.c --- a/drivers/net/ethernet/ralink/esw_rt3052.c
+++ b/drivers/net/ethernet/ralink/esw_rt3052.c +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
@@ -98,8 +98,8 @@
rt305x_mii_write(esw, 0, 29, 0x598b); rt305x_mii_write(esw, 0, 29, 0x598b);
/* select local register */ /* select local register */
rt305x_mii_write(esw, 0, 31, 0x8000); rt305x_mii_write(esw, 0, 31, 0x8000);
- } else if (ralink_soc == MT762X_SOC_MT7628AN) { - } else if (mt762x_soc == MT762X_SOC_MT7628AN) {
+ } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { + } else if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
int i; int i;
// u32 phy_val; // u32 phy_val;
u32 val; u32 val;
@@ -107,8 +107,8 @@
int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
u32 reg; u32 reg;
- if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN)) - if ((mt762x_soc != RT305X_SOC_RT5350) && (mt762x_soc != MT762X_SOC_MT7628AN))
+ if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688)) + if ((mt762x_soc != RT305X_SOC_RT5350) && (mt762x_soc != MT762X_SOC_MT7628AN) && (mt762x_soc != MT762X_SOC_MT7688))
return -EINVAL; return -EINVAL;
if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)