lots of ifxmips cleanups
SVN-Revision: 11607
This commit is contained in:
		@@ -0,0 +1,3 @@
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					[ "$ACTION" = "released" -a "$BUTTON" = reset ] && {
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						reboot
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					}
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@@ -82,6 +82,7 @@ CONFIG_HW_RANDOM=y
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# CONFIG_IDE is not set
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					# CONFIG_IDE is not set
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CONFIG_IFXMIPS=y
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					CONFIG_IFXMIPS=y
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CONFIG_IFXMIPS_EEPROM=y
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					CONFIG_IFXMIPS_EEPROM=y
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					CONFIG_IFXMIPS_GPIO_RST_BTN=y
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CONFIG_IFXMIPS_MEI=y
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					CONFIG_IFXMIPS_MEI=y
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CONFIG_IFXMIPS_MII0=y
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					CONFIG_IFXMIPS_MII0=y
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# CONFIG_IFXMIPS_PROM_ASC0 is not set
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					# CONFIG_IFXMIPS_PROM_ASC0 is not set
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@@ -18,6 +18,10 @@ config IFXMIPS_MEI
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	bool "IFXMips mei"
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						bool "IFXMips mei"
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	default y
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						default y
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					config IFXMIPS_GPIO_RST_BTN
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						bool "Reset Button"
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						default y
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choice
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					choice
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	prompt "prom_printf ASC"
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						prompt "prom_printf ASC"
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	help
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						help
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@@ -30,7 +30,9 @@
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#include <asm/time.h>
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					#include <asm/time.h>
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#include <asm/irq.h>
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					#include <asm/irq.h>
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#include <asm/io.h>
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					#include <asm/io.h>
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					#include <linux/etherdevice.h>
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#include <asm/ifxmips/ifxmips.h>
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					#include <asm/ifxmips/ifxmips.h>
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					#include <asm/ifxmips/ifxmips_mii0.h>
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#define MAX_IFXMIPS_DEVS		9
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					#define MAX_IFXMIPS_DEVS		9
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@@ -42,10 +44,13 @@
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static unsigned int chiprev;
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					static unsigned int chiprev;
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static struct platform_device *ifxmips_devs[MAX_IFXMIPS_DEVS];
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					static struct platform_device *ifxmips_devs[MAX_IFXMIPS_DEVS];
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					static int cmdline_mac = 0;
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spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED;
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					spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED;
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EXPORT_SYMBOL_GPL(ebu_lock);
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					EXPORT_SYMBOL_GPL(ebu_lock);
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					static struct ifxmips_mac ifxmips_mii_mac;
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static struct platform_device
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					static struct platform_device
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ifxmips_led[] =
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					ifxmips_led[] =
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{
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					{
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@@ -70,6 +75,9 @@ ifxmips_mii[] =
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	{
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						{
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		.id = 0,
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							.id = 0,
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		.name = "ifxmips_mii0",
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							.name = "ifxmips_mii0",
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							.dev = {
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								.platform_data = &ifxmips_mii_mac,
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							}
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	},
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						},
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};
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					};
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@@ -82,11 +90,6 @@ ifxmips_wdt[] =
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	},
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						},
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};
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					};
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static struct physmap_flash_data
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ifxmips_mtd_data = {
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	.width    = 2,
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};
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static struct resource
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					static struct resource
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ifxmips_mtd_resource = {
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					ifxmips_mtd_resource = {
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	.start  = IFXMIPS_FLASH_START,
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						.start  = IFXMIPS_FLASH_START,
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@@ -100,9 +103,6 @@ ifxmips_mtd[] =
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	{
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						{
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		.id = 0,
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							.id = 0,
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		.name = "ifxmips_mtd",
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							.name = "ifxmips_mtd",
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		.dev = {
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			.platform_data = &ifxmips_mtd_data,
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		},
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		.num_resources  = 1,
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							.num_resources  = 1,
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		.resource   = &ifxmips_mtd_resource,
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							.resource   = &ifxmips_mtd_resource,
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	},
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						},
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@@ -148,11 +148,40 @@ get_system_type(void)
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	return BOARD_SYSTEM_TYPE;
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						return BOARD_SYSTEM_TYPE;
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}
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					}
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					#define IS_HEX(x)	(((x >='0' && x <= '9') || (x >='a' && x <= 'f') || (x >='A' && x <= 'F'))?(1):(0))
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					static int __init
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					ifxmips_set_mii0_mac(char *str)
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					{
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						int i;
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						str = strchr(str, '=');
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						if(!str)
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							goto out;
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						str++;
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						if(strlen(str) != 17)
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							goto out;
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						for(i = 0; i < 6; i++)
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						{
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							if(!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1]))
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								goto out;
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							if((i != 5) && (str[(3 * i) + 2] != ':'))
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								goto out;
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							ifxmips_mii_mac.mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
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						}
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						if(is_valid_ether_addr(ifxmips_mii_mac.mac))
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							cmdline_mac = 1;
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					out:
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						return 1;
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					}
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					__setup("mii0_mac", ifxmips_set_mii0_mac);
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int __init
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					int __init
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ifxmips_init_devices(void)
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					ifxmips_init_devices(void)
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{
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					{
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	int dev = 0;
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						int dev = 0;
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						if(!cmdline_mac)
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							random_ether_addr(ifxmips_mii_mac.mac);
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	ifxmips_devs[dev++] = ifxmips_led;
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						ifxmips_devs[dev++] = ifxmips_led;
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	ifxmips_devs[dev++] = ifxmips_gpio;
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						ifxmips_devs[dev++] = ifxmips_gpio;
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	ifxmips_devs[dev++] = ifxmips_mii;
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						ifxmips_devs[dev++] = ifxmips_mii;
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@@ -429,3 +429,46 @@ void cgu_setup_pci_clk(int external_clock)
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		ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
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							ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
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	}
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						}
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}
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					}
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					unsigned int
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					ifxmips_get_ddr_hz(void)
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					{
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						switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
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						{
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						case 0:
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							return CLOCK_167M;
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						case 1:
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							return CLOCK_133M;
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						case 2:
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							return CLOCK_111M;
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						}
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						return CLOCK_83M;
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					}
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					EXPORT_SYMBOL(ifxmips_get_ddr_hz);
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					unsigned int
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					ifxmips_get_cpu_hz(void)
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					{
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						unsigned int ddr_clock = ifxmips_get_ddr_hz();
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						switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
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						{
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						case 0:
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							return CLOCK_333M;
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						case 4:
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							return ddr_clock;
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						}
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						return ddr_clock << 1;
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					}
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					EXPORT_SYMBOL(ifxmips_get_cpu_hz);
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					unsigned int
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					ifxmips_get_fpi_hz(void)
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					{
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						unsigned int ddr_clock = ifxmips_get_ddr_hz();
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						if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
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							return ddr_clock >> 1;
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						return ddr_clock;
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					}
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					EXPORT_SYMBOL(ifxmips_get_fpi_hz);
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@@ -303,7 +303,7 @@ reset_button_poll(unsigned long unused)
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{
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					{
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	struct event_t *event;
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						struct event_t *event;
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	rst_button_timer.expires = jiffies + HZ;
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						rst_button_timer.expires = jiffies + (HZ / 4);
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	add_timer(&rst_button_timer);
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						add_timer(&rst_button_timer);
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	if (pressed != ifxmips_port_get_input(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN))
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						if (pressed != ifxmips_port_get_input(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN))
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@@ -312,7 +312,6 @@ reset_button_poll(unsigned long unused)
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			pressed = 0;
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								pressed = 0;
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		else
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							else
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			pressed = 1;
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								pressed = 1;
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		printk("reset button was %s\n", (pressed ? "pressed" : "released"));
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		event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
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							event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
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		if (!event)
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							if (!event)
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		{
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							{
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@@ -141,6 +141,7 @@ ifxmips_hw_irqdispatch(int module)
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	if(irq == 0)
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						if(irq == 0)
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		return;
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							return;
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						/* we need to do this due to a silicon bug */
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	irq = ls1bit32(irq);
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						irq = ls1bit32(irq);
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	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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						do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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@@ -27,6 +27,7 @@
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#include <asm/ifxmips/ifxmips.h>
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					#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_irq.h>
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					#include <asm/ifxmips/ifxmips_irq.h>
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#include <asm/ifxmips/ifxmips_pmu.h>
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					#include <asm/ifxmips/ifxmips_pmu.h>
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					#include <asm/ifxmips/ifxmips_cgu.h>
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#include <asm/ifxmips/ifxmips_prom.h>
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					#include <asm/ifxmips/ifxmips_prom.h>
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static unsigned int r4k_offset;
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					static unsigned int r4k_offset;
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@@ -34,51 +35,10 @@ static unsigned int r4k_cur;
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extern void ifxmips_reboot_setup(void);
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					extern void ifxmips_reboot_setup(void);
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unsigned int
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					 | 
				
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ifxmips_get_ddr_hz(void)
 | 
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{
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					 | 
				
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	switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
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					 | 
				
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	{
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	case 0:
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		return CLOCK_167M;
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	case 1:
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		return CLOCK_133M;
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					 | 
				
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	case 2:
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		return CLOCK_111M;
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					 | 
				
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	}
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					 | 
				
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	return CLOCK_83M;
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					 | 
				
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}
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EXPORT_SYMBOL(ifxmips_get_ddr_hz);
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unsigned int
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ifxmips_get_cpu_hz(void)
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					 | 
				
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{
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					 | 
				
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	unsigned int ddr_clock = ifxmips_get_ddr_hz();
 | 
					 | 
				
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	switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
 | 
					 | 
				
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	{
 | 
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	case 0:
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		return CLOCK_333M;
 | 
					 | 
				
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	case 4:
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					 | 
				
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		return ddr_clock;
 | 
					 | 
				
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	}
 | 
					 | 
				
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	return ddr_clock << 1;
 | 
					 | 
				
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}
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EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 | 
					 | 
				
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					 | 
				
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unsigned int
 | 
					 | 
				
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ifxmips_get_fpi_hz(void)
 | 
					 | 
				
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{
 | 
					 | 
				
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	unsigned int ddr_clock = ifxmips_get_ddr_hz();
 | 
					 | 
				
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	if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
 | 
					 | 
				
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		return ddr_clock >> 1;
 | 
					 | 
				
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	return ddr_clock;
 | 
					 | 
				
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}
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EXPORT_SYMBOL(ifxmips_get_fpi_hz);
 | 
					 | 
				
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					 | 
				
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unsigned int
 | 
					unsigned int
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ifxmips_get_cpu_ver(void)
 | 
					ifxmips_get_cpu_ver(void)
 | 
				
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{
 | 
					{
 | 
				
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	return ifxmips_r32(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
 | 
						return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28;
 | 
				
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}
 | 
					}
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EXPORT_SYMBOL(ifxmips_get_cpu_ver);
 | 
					EXPORT_SYMBOL(ifxmips_get_cpu_ver);
 | 
				
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 | 
					
 | 
				
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@@ -100,27 +60,15 @@ ifxmips_get_counter_resolution(void)
 | 
				
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		return res;
 | 
							return res;
 | 
				
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}
 | 
					}
 | 
				
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 | 
					
 | 
				
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int
 | 
					 | 
				
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ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
 | 
					 | 
				
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{
 | 
					 | 
				
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	/*TODO*/
 | 
					 | 
				
			||||||
	printk(KERN_ERR "TODO: BUS error\n");
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
	return MIPS_BE_FATAL;
 | 
					 | 
				
			||||||
}
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
void __init
 | 
					void __init
 | 
				
			||||||
plat_time_init(void)
 | 
					plat_time_init(void)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
	mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
 | 
						mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
 | 
				
			||||||
	r4k_cur = (read_c0_count() + r4k_offset);
 | 
						r4k_cur = (read_c0_count() + r4k_offset);
 | 
				
			||||||
	write_c0_compare(r4k_cur);
 | 
						write_c0_compare(r4k_cur);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
 | 
						ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
 | 
				
			||||||
 | 
						ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); // set clock divider to 1
 | 
				
			||||||
	ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC);
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
	ifxmips_w32(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
 | 
					 | 
				
			||||||
	ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
 | 
					 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
void __init
 | 
					void __init
 | 
				
			||||||
@@ -134,7 +82,6 @@ plat_mem_setup(void)
 | 
				
			|||||||
	write_c0_status(status);
 | 
						write_c0_status(status);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ifxmips_reboot_setup();
 | 
						ifxmips_reboot_setup();
 | 
				
			||||||
	board_be_handler = &ifxmips_be_handler;
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ioport_resource.start = IOPORT_RESOURCE_START;
 | 
						ioport_resource.start = IOPORT_RESOURCE_START;
 | 
				
			||||||
	ioport_resource.end = IOPORT_RESOURCE_END;
 | 
						ioport_resource.end = IOPORT_RESOURCE_END;
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -31,7 +31,6 @@
 | 
				
			|||||||
#include <linux/magic.h>
 | 
					#include <linux/magic.h>
 | 
				
			||||||
#include <linux/platform_device.h>
 | 
					#include <linux/platform_device.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					 | 
				
			||||||
static struct map_info
 | 
					static struct map_info
 | 
				
			||||||
ifxmips_map = {
 | 
					ifxmips_map = {
 | 
				
			||||||
	.name = "ifxmips_mtd",
 | 
						.name = "ifxmips_mtd",
 | 
				
			||||||
@@ -46,7 +45,7 @@ ifxmips_read16(struct map_info * map, unsigned long adr)
 | 
				
			|||||||
	map_word temp;
 | 
						map_word temp;
 | 
				
			||||||
	spin_lock_irqsave(&ebu_lock, flags);
 | 
						spin_lock_irqsave(&ebu_lock, flags);
 | 
				
			||||||
	adr ^= 2;
 | 
						adr ^= 2;
 | 
				
			||||||
	temp.x[0] = *((__u16 *) (map->virt + adr));
 | 
						temp.x[0] = *((__u16*)(map->virt + adr));
 | 
				
			||||||
	spin_unlock_irqrestore(&ebu_lock, flags);
 | 
						spin_unlock_irqrestore(&ebu_lock, flags);
 | 
				
			||||||
	return temp;
 | 
						return temp;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
@@ -57,7 +56,7 @@ ifxmips_write16(struct map_info *map, map_word d, unsigned long adr)
 | 
				
			|||||||
	unsigned long flags;
 | 
						unsigned long flags;
 | 
				
			||||||
	spin_lock_irqsave(&ebu_lock, flags);
 | 
						spin_lock_irqsave(&ebu_lock, flags);
 | 
				
			||||||
	adr ^= 2;
 | 
						adr ^= 2;
 | 
				
			||||||
	*((__u16 *) (map->virt + adr)) = d.x[0];
 | 
						*((__u16*)(map->virt + adr)) = d.x[0];
 | 
				
			||||||
	spin_unlock_irqrestore(&ebu_lock, flags);
 | 
						spin_unlock_irqrestore(&ebu_lock, flags);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -73,7 +72,7 @@ ifxmips_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t le
 | 
				
			|||||||
	to_8 = (unsigned char*) to;
 | 
						to_8 = (unsigned char*) to;
 | 
				
			||||||
	while(len--)
 | 
						while(len--)
 | 
				
			||||||
		*to_8++ = *p++;
 | 
							*to_8++ = *p++;
 | 
				
			||||||
		spin_unlock_irqrestore(&ebu_lock, flags);
 | 
						spin_unlock_irqrestore(&ebu_lock, flags);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
void
 | 
					void
 | 
				
			||||||
@@ -85,9 +84,8 @@ ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_
 | 
				
			|||||||
	spin_lock_irqsave(&ebu_lock, flags);
 | 
						spin_lock_irqsave(&ebu_lock, flags);
 | 
				
			||||||
	to += (unsigned long) map->virt;
 | 
						to += (unsigned long) map->virt;
 | 
				
			||||||
	to_8 = (unsigned char*)to;
 | 
						to_8 = (unsigned char*)to;
 | 
				
			||||||
	while(len--){
 | 
						while(len--)
 | 
				
			||||||
		*p++ = *to_8++;
 | 
							*p++ = *to_8++;
 | 
				
			||||||
	}
 | 
					 | 
				
			||||||
	spin_unlock_irqrestore(&ebu_lock, flags);
 | 
						spin_unlock_irqrestore(&ebu_lock, flags);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -118,7 +116,6 @@ ifxmips_partitions[4] = {
 | 
				
			|||||||
int
 | 
					int
 | 
				
			||||||
find_uImage_size(unsigned long start_offset){
 | 
					find_uImage_size(unsigned long start_offset){
 | 
				
			||||||
	unsigned long temp;
 | 
						unsigned long temp;
 | 
				
			||||||
 | 
					 | 
				
			||||||
	ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4);
 | 
						ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4);
 | 
				
			||||||
	printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40);
 | 
						printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40);
 | 
				
			||||||
	return temp + 0x40;
 | 
						return temp + 0x40;
 | 
				
			||||||
@@ -127,9 +124,7 @@ find_uImage_size(unsigned long start_offset){
 | 
				
			|||||||
int
 | 
					int
 | 
				
			||||||
detect_squashfs_partition(unsigned long start_offset){
 | 
					detect_squashfs_partition(unsigned long start_offset){
 | 
				
			||||||
	unsigned long temp;
 | 
						unsigned long temp;
 | 
				
			||||||
 | 
					 | 
				
			||||||
	ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 4);
 | 
						ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 4);
 | 
				
			||||||
 | 
					 | 
				
			||||||
	return (temp == SQUASHFS_MAGIC);
 | 
						return (temp == SQUASHFS_MAGIC);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -146,10 +141,10 @@ ifxmips_mtd_probe(struct platform_device *dev)
 | 
				
			|||||||
	ifxmips_map.write = ifxmips_write16;
 | 
						ifxmips_map.write = ifxmips_write16;
 | 
				
			||||||
	ifxmips_map.copy_from = ifxmips_copy_from;
 | 
						ifxmips_map.copy_from = ifxmips_copy_from;
 | 
				
			||||||
	ifxmips_map.copy_to = ifxmips_copy_to;
 | 
						ifxmips_map.copy_to = ifxmips_copy_to;
 | 
				
			||||||
 | 
						ifxmips_map.phys = dev->resource->start;
 | 
				
			||||||
 | 
						ifxmips_map.size = dev->resource->end - ifxmips_map.phys + 1;
 | 
				
			||||||
 | 
						ifxmips_map.virt = ioremap_nocache(ifxmips_map.phys, ifxmips_map.size);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ifxmips_map.phys = IFXMIPS_FLASH_START;
 | 
					 | 
				
			||||||
	ifxmips_map.virt = ioremap_nocache(IFXMIPS_FLASH_START, IFXMIPS_FLASH_MAX);
 | 
					 | 
				
			||||||
	ifxmips_map.size = IFXMIPS_FLASH_MAX;
 | 
					 | 
				
			||||||
	if(!ifxmips_map.virt)
 | 
						if(!ifxmips_map.virt)
 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n");
 | 
							printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n");
 | 
				
			||||||
@@ -165,7 +160,6 @@ ifxmips_mtd_probe(struct platform_device *dev)
 | 
				
			|||||||
	}
 | 
						}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ifxmips_mtd->owner = THIS_MODULE;
 | 
						ifxmips_mtd->owner = THIS_MODULE;
 | 
				
			||||||
 | 
					 | 
				
			||||||
	uimage_size = find_uImage_size(ifxmips_partitions[2].offset);
 | 
						uimage_size = find_uImage_size(ifxmips_partitions[2].offset);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	if(detect_squashfs_partition(ifxmips_partitions[2].offset + uimage_size))
 | 
						if(detect_squashfs_partition(ifxmips_partitions[2].offset + uimage_size))
 | 
				
			||||||
@@ -205,8 +199,7 @@ init_ifxmips_mtd(void)
 | 
				
			|||||||
	return ret;
 | 
						return ret;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static void
 | 
					static void __exit
 | 
				
			||||||
__exit
 | 
					 | 
				
			||||||
cleanup_ifxmips_mtd(void)
 | 
					cleanup_ifxmips_mtd(void)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
	platform_driver_unregister(&ifxmips_mtd_driver);
 | 
						platform_driver_unregister(&ifxmips_mtd_driver);
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -40,10 +40,8 @@
 | 
				
			|||||||
#include <asm/ifxmips/ifxmips_dma.h>
 | 
					#include <asm/ifxmips/ifxmips_dma.h>
 | 
				
			||||||
#include <asm/ifxmips/ifxmips_pmu.h>
 | 
					#include <asm/ifxmips/ifxmips_pmu.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define DRVNAME		"ifxmips_mii0"
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
static struct net_device *ifxmips_mii0_dev;
 | 
					static struct net_device *ifxmips_mii0_dev;
 | 
				
			||||||
static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
 | 
					static unsigned char mac_addr[MAX_ADDR_LEN];
 | 
				
			||||||
 | 
					
 | 
				
			||||||
void
 | 
					void
 | 
				
			||||||
ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data)
 | 
					ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data)
 | 
				
			||||||
@@ -110,7 +108,7 @@ ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev)
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
	if(len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
 | 
						if(len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": packet too large %d\n",len);
 | 
							printk(KERN_INFO "ifxmips_mii0: packet too large %d\n",len);
 | 
				
			||||||
		goto ifxmips_mii_hw_receive_err_exit;
 | 
							goto ifxmips_mii_hw_receive_err_exit;
 | 
				
			||||||
	}
 | 
						}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -118,13 +116,13 @@ ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev)
 | 
				
			|||||||
	len -= 4;
 | 
						len -= 4;
 | 
				
			||||||
	if(skb == NULL)
 | 
						if(skb == NULL)
 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": cannot restore pointer\n");
 | 
							printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n");
 | 
				
			||||||
		goto ifxmips_mii_hw_receive_err_exit;
 | 
							goto ifxmips_mii_hw_receive_err_exit;
 | 
				
			||||||
	}
 | 
						}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	if(len > (skb->end - skb->tail))
 | 
						if(len > (skb->end - skb->tail))
 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n",
 | 
							printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n",
 | 
				
			||||||
			(len+4), skb->end, skb->tail);
 | 
								(len+4), skb->end, skb->tail);
 | 
				
			||||||
		goto ifxmips_mii_hw_receive_err_exit;
 | 
							goto ifxmips_mii_hw_receive_err_exit;
 | 
				
			||||||
	}
 | 
						}
 | 
				
			||||||
@@ -157,9 +155,7 @@ ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev)
 | 
				
			|||||||
	int ret = 0;
 | 
						int ret = 0;
 | 
				
			||||||
	struct ifxmips_mii_priv *priv = dev->priv;
 | 
						struct ifxmips_mii_priv *priv = dev->priv;
 | 
				
			||||||
	struct dma_device_info* dma_dev = priv->dma_device;
 | 
						struct dma_device_info* dma_dev = priv->dma_device;
 | 
				
			||||||
 | 
					 | 
				
			||||||
	ret = dma_device_write(dma_dev, buf, len, priv->skb);
 | 
						ret = dma_device_write(dma_dev, buf, len, priv->skb);
 | 
				
			||||||
 | 
					 | 
				
			||||||
	return ret;
 | 
						return ret;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -219,7 +215,7 @@ dma_intr_handler(struct dma_device_info* dma_dev, int status)
 | 
				
			|||||||
		break;
 | 
							break;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	case TX_BUF_FULL_INT:
 | 
						case TX_BUF_FULL_INT:
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": tx buffer full\n");
 | 
							printk(KERN_INFO "ifxmips_mii0: tx buffer full\n");
 | 
				
			||||||
		netif_stop_queue(ifxmips_mii0_dev);
 | 
							netif_stop_queue(ifxmips_mii0_dev);
 | 
				
			||||||
		for (i = 0; i < dma_dev->max_tx_chan_num; i++)
 | 
							for (i = 0; i < dma_dev->max_tx_chan_num; i++)
 | 
				
			||||||
		{
 | 
							{
 | 
				
			||||||
@@ -280,12 +276,11 @@ ifxmips_get_stats(struct net_device *dev)
 | 
				
			|||||||
static int
 | 
					static int
 | 
				
			||||||
ifxmips_mii_dev_init(struct net_device *dev)
 | 
					ifxmips_mii_dev_init(struct net_device *dev)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
	u64 retval = 0;
 | 
					 | 
				
			||||||
	int i;
 | 
						int i;
 | 
				
			||||||
	struct ifxmips_mii_priv *priv;
 | 
						struct ifxmips_mii_priv *priv;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ether_setup(dev);
 | 
						ether_setup(dev);
 | 
				
			||||||
	printk(KERN_INFO DRVNAME ": %s is up\n", dev->name);
 | 
						printk(KERN_INFO "ifxmips_mii0: %s is up\n", dev->name);
 | 
				
			||||||
	dev->open = ifxmips_ifxmips_mii_open;
 | 
						dev->open = ifxmips_ifxmips_mii_open;
 | 
				
			||||||
	dev->stop = ifxmips_mii_release;
 | 
						dev->stop = ifxmips_mii_release;
 | 
				
			||||||
	dev->hard_start_xmit = ifxmips_mii_tx;
 | 
						dev->hard_start_xmit = ifxmips_mii_tx;
 | 
				
			||||||
@@ -318,26 +313,12 @@ ifxmips_mii_dev_init(struct net_device *dev)
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
	dma_device_register(priv->dma_device);
 | 
						dma_device_register(priv->dma_device);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	/*read the mac address from the mac table and put them into the mac table.*/
 | 
						printk(KERN_INFO "ifxmips_mii0: using mac=");
 | 
				
			||||||
	for (i = 0; i < 6; i++)
 | 
						for(i = 0; i < 6; i++)
 | 
				
			||||||
		retval += u_boot_ethaddr[i];
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
	//TODO
 | 
					 | 
				
			||||||
	/* ethaddr not set in u-boot ? */
 | 
					 | 
				
			||||||
	if(retval == 0)
 | 
					 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": using default MAC address\n");
 | 
							dev->dev_addr[i] = mac_addr[i];
 | 
				
			||||||
		dev->dev_addr[0] = 0x00;
 | 
							printk("%02X%c", dev->dev_addr[i], (i == 5)?('\n'):(':'));
 | 
				
			||||||
		dev->dev_addr[1] = 0x11;
 | 
					 | 
				
			||||||
		dev->dev_addr[2] = 0x22;
 | 
					 | 
				
			||||||
		dev->dev_addr[3] = 0x33;
 | 
					 | 
				
			||||||
		dev->dev_addr[4] = 0x44;
 | 
					 | 
				
			||||||
		dev->dev_addr[5] = 0x55;
 | 
					 | 
				
			||||||
	} else {
 | 
					 | 
				
			||||||
		for(i = 0; i < 6; i++)
 | 
					 | 
				
			||||||
			dev->dev_addr[i] = u_boot_ethaddr[i];
 | 
					 | 
				
			||||||
	}
 | 
						}
 | 
				
			||||||
 | 
					 | 
				
			||||||
	return 0;
 | 
						return 0;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -348,9 +329,9 @@ ifxmips_mii_chip_init(int mode)
 | 
				
			|||||||
	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
 | 
						ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	if(mode == REV_MII_MODE)
 | 
						if(mode == REV_MII_MODE)
 | 
				
			||||||
		ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
 | 
							ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
 | 
				
			||||||
	else if(mode == MII_MODE)
 | 
						else if(mode == MII_MODE)
 | 
				
			||||||
		ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
 | 
							ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
 | 
				
			||||||
	ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
 | 
						ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
 | 
				
			||||||
	ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
 | 
						ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
 | 
				
			||||||
	wmb();
 | 
						wmb();
 | 
				
			||||||
@@ -360,20 +341,20 @@ static int
 | 
				
			|||||||
ifxmips_mii_probe(struct platform_device *dev)
 | 
					ifxmips_mii_probe(struct platform_device *dev)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
	int result = 0;
 | 
						int result = 0;
 | 
				
			||||||
 | 
						struct ifxmips_mac *mac = (struct ifxmips_mac*)dev->dev.platform_data;
 | 
				
			||||||
	ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
 | 
						ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
 | 
				
			||||||
	ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
 | 
						ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
 | 
				
			||||||
 | 
						memcpy(mac_addr, mac->mac, 6);
 | 
				
			||||||
	strcpy(ifxmips_mii0_dev->name, "eth%d");
 | 
						strcpy(ifxmips_mii0_dev->name, "eth%d");
 | 
				
			||||||
	result = register_netdev(ifxmips_mii0_dev);
 | 
						result = register_netdev(ifxmips_mii0_dev);
 | 
				
			||||||
	if (result)
 | 
						if (result)
 | 
				
			||||||
	{
 | 
						{
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
 | 
							printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
 | 
				
			||||||
		goto out;
 | 
							goto out;
 | 
				
			||||||
	}
 | 
						}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	/* ifxmips eval kit connects the phy/switch in REV mode */
 | 
					 | 
				
			||||||
	ifxmips_mii_chip_init(REV_MII_MODE);
 | 
						ifxmips_mii_chip_init(REV_MII_MODE);
 | 
				
			||||||
	printk(KERN_INFO DRVNAME ": driver loaded!\n");
 | 
						printk(KERN_INFO "ifxmips_mii0: driver loaded!\n");
 | 
				
			||||||
 | 
					
 | 
				
			||||||
out:
 | 
					out:
 | 
				
			||||||
	return result;
 | 
						return result;
 | 
				
			||||||
@@ -384,7 +365,7 @@ ifxmips_mii_remove(struct platform_device *dev)
 | 
				
			|||||||
{
 | 
					{
 | 
				
			||||||
	struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv;
 | 
						struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	printk(KERN_INFO DRVNAME ": ifxmips_mii0 cleanup\n");
 | 
						printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n");
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	dma_device_unregister(priv->dma_device);
 | 
						dma_device_unregister(priv->dma_device);
 | 
				
			||||||
	dma_device_release(priv->dma_device);
 | 
						dma_device_release(priv->dma_device);
 | 
				
			||||||
@@ -399,7 +380,7 @@ platform_driver ifxmips_mii_driver = {
 | 
				
			|||||||
	.probe = ifxmips_mii_probe,
 | 
						.probe = ifxmips_mii_probe,
 | 
				
			||||||
	.remove = ifxmips_mii_remove,
 | 
						.remove = ifxmips_mii_remove,
 | 
				
			||||||
	.driver = {
 | 
						.driver = {
 | 
				
			||||||
		.name = DRVNAME,
 | 
							.name = "ifxmips_mii0",
 | 
				
			||||||
		.owner = THIS_MODULE,
 | 
							.owner = THIS_MODULE,
 | 
				
			||||||
	},
 | 
						},
 | 
				
			||||||
};
 | 
					};
 | 
				
			||||||
@@ -409,7 +390,7 @@ ifxmips_mii_init(void)
 | 
				
			|||||||
{
 | 
					{
 | 
				
			||||||
	int ret = platform_driver_register(&ifxmips_mii_driver);
 | 
						int ret = platform_driver_register(&ifxmips_mii_driver);
 | 
				
			||||||
	if (ret)
 | 
						if (ret)
 | 
				
			||||||
		printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
 | 
							printk(KERN_INFO "ifxmips_mii0: Error registering platfom driver!");
 | 
				
			||||||
	return ret;
 | 
						return ret;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -133,7 +133,7 @@ static int ifxmips_wdt_release(struct inode *inode, struct file *file)
 | 
				
			|||||||
		ifxmips_wdt_disable();
 | 
							ifxmips_wdt_disable();
 | 
				
			||||||
	else
 | 
						else
 | 
				
			||||||
#endif
 | 
					#endif
 | 
				
			||||||
		printk(KERN_INFO "watchdog closed without warning, rebooting system\n");
 | 
							printk("ifxmips_wdt: watchdog closed without warning, rebooting system\n");
 | 
				
			||||||
	return 0;
 | 
						return 0;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -22,6 +22,7 @@
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
#define ifxmips_r32(reg) __raw_readl(reg)
 | 
					#define ifxmips_r32(reg) __raw_readl(reg)
 | 
				
			||||||
#define ifxmips_w32(val,reg) __raw_writel(val,reg)
 | 
					#define ifxmips_w32(val,reg) __raw_writel(val,reg)
 | 
				
			||||||
 | 
					#define ifxmips_w32_mask(clear,set,reg)	ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
/*------------ GENERAL */
 | 
					/*------------ GENERAL */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -87,13 +88,6 @@
 | 
				
			|||||||
#define IFXMIPS_RCU_RST_REQ_AFE	(1 << 11)
 | 
					#define IFXMIPS_RCU_RST_REQ_AFE	(1 << 11)
 | 
				
			||||||
#define IFXMIPS_RCU_RST_REQ_ARC_JTAG	(1 << 20)
 | 
					#define IFXMIPS_RCU_RST_REQ_ARC_JTAG	(1 << 20)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
/*------------ MCD */
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define IFXMIPS_MCD_BASE_ADDR	(KSEG1 + 0x1F106000)
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/* chip id */
 | 
					 | 
				
			||||||
#define IFXMIPS_MCD_CHIPID		((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
/*------------ GPTU */
 | 
					/*------------ GPTU */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -9,4 +9,7 @@ u32 cgu_get_ethernet_clock(int mii);
 | 
				
			|||||||
u32 cgu_get_usb_clock(void);
 | 
					u32 cgu_get_usb_clock(void);
 | 
				
			||||||
u32 cgu_get_clockout(int clkout);
 | 
					u32 cgu_get_clockout(int clkout);
 | 
				
			||||||
void cgu_setup_pci_clk(int internal_clock);
 | 
					void cgu_setup_pci_clk(int internal_clock);
 | 
				
			||||||
 | 
					u32 ifxmips_get_ddr_hz(void);
 | 
				
			||||||
 | 
					u32 ifxmips_get_cpu_hz(void);
 | 
				
			||||||
 | 
					u32 ifxmips_get_fpi_hz(void);
 | 
				
			||||||
#endif
 | 
					#endif
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,254 +1,34 @@
 | 
				
			|||||||
#ifndef IFXMIPS_SW_H
 | 
					#ifndef IFXMIPS_MII0_H
 | 
				
			||||||
#define IFXMIPS_SW_H
 | 
					#define IFXMIPS_MII0_H
 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/******************************************************************************
 | 
					 | 
				
			||||||
**
 | 
					 | 
				
			||||||
** FILE NAME    : ifxmips_sw.h
 | 
					 | 
				
			||||||
** PROJECT      : IFXMips
 | 
					 | 
				
			||||||
** MODULES     	: ETH Interface (MII0)
 | 
					 | 
				
			||||||
**
 | 
					 | 
				
			||||||
** DATE         : 11 AUG 2005
 | 
					 | 
				
			||||||
** AUTHOR       : Wu Qi Ming
 | 
					 | 
				
			||||||
** DESCRIPTION  : ETH Interface (MII0) Driver Header File
 | 
					 | 
				
			||||||
** COPYRIGHT    : 	Copyright (c) 2006
 | 
					 | 
				
			||||||
**			Infineon Technologies AG
 | 
					 | 
				
			||||||
**			Am Campeon 1-12, 85579 Neubiberg, Germany
 | 
					 | 
				
			||||||
**
 | 
					 | 
				
			||||||
**    This program is free software; you can redistribute it and/or modify
 | 
					 | 
				
			||||||
**    it under the terms of the GNU General Public License as published by
 | 
					 | 
				
			||||||
**    the Free Software Foundation; either version 2 of the License, or
 | 
					 | 
				
			||||||
**    (at your option) any later version.
 | 
					 | 
				
			||||||
**
 | 
					 | 
				
			||||||
** HISTORY
 | 
					 | 
				
			||||||
** $Date        $Author         $Comment
 | 
					 | 
				
			||||||
** 11 AUG 2005  Wu Qi Ming      Initiate Version
 | 
					 | 
				
			||||||
** 23 OCT 2006  Xu Liang        Add GPL header.
 | 
					 | 
				
			||||||
*******************************************************************************/
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define SET_ETH_SPEED_AUTO   SIOCDEVPRIVATE
 | 
					 | 
				
			||||||
#define SET_ETH_SPEED_10     SIOCDEVPRIVATE+1
 | 
					 | 
				
			||||||
#define SET_ETH_SPEED_100    SIOCDEVPRIVATE+2
 | 
					 | 
				
			||||||
#define SET_ETH_DUPLEX_AUTO  SIOCDEVPRIVATE+3
 | 
					 | 
				
			||||||
#define SET_ETH_DUPLEX_HALF  SIOCDEVPRIVATE+4
 | 
					 | 
				
			||||||
#define SET_ETH_DUPLEX_FULL  SIOCDEVPRIVATE+5
 | 
					 | 
				
			||||||
#define SET_ETH_REG          SIOCDEVPRIVATE+6
 | 
					 | 
				
			||||||
#define VLAN_TOOLS           SIOCDEVPRIVATE+7
 | 
					 | 
				
			||||||
#define MAC_TABLE_TOOLS      SIOCDEVPRIVATE+8
 | 
					 | 
				
			||||||
#define SET_VLAN_COS         SIOCDEVPRIVATE+9
 | 
					 | 
				
			||||||
#define SET_DSCP_COS         SIOCDEVPRIVATE+10
 | 
					 | 
				
			||||||
#define ENABLE_VLAN_CLASSIFICATION    SIOCDEVPRIVATE+11
 | 
					 | 
				
			||||||
#define DISABLE_VLAN_CLASSIFICATION   SIOCDEVPRIVATE+12
 | 
					 | 
				
			||||||
#define VLAN_CLASS_FIRST              SIOCDEVPRIVATE+13
 | 
					 | 
				
			||||||
#define VLAN_CLASS_SECOND             SIOCDEVPRIVATE+14
 | 
					 | 
				
			||||||
#define ENABLE_DSCP_CLASSIFICATION    SIOCDEVPRIVATE+15
 | 
					 | 
				
			||||||
#define DISABLE_DSCP_CLASSIFICATION   SIOCDEVPRIVATE+16
 | 
					 | 
				
			||||||
#define PASS_UNICAST_PACKETS          SIOCDEVPRIVATE+17
 | 
					 | 
				
			||||||
#define FILTER_UNICAST_PACKETS        SIOCDEVPRIVATE+18
 | 
					 | 
				
			||||||
#define KEEP_BROADCAST_PACKETS        SIOCDEVPRIVATE+19
 | 
					 | 
				
			||||||
#define DROP_BROADCAST_PACKETS        SIOCDEVPRIVATE+20
 | 
					 | 
				
			||||||
#define KEEP_MULTICAST_PACKETS        SIOCDEVPRIVATE+21
 | 
					 | 
				
			||||||
#define DROP_MULTICAST_PACKETS        SIOCDEVPRIVATE+22
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*===mac table commands==*/
 | 
					 | 
				
			||||||
#define RESET_MAC_TABLE     0
 | 
					 | 
				
			||||||
#define READ_MAC_ENTRY    1
 | 
					 | 
				
			||||||
#define WRITE_MAC_ENTRY   2
 | 
					 | 
				
			||||||
#define ADD_MAC_ENTRY     3
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*====vlan commands===*/
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define CHANGE_VLAN_CTRL     0
 | 
					 | 
				
			||||||
#define READ_VLAN_ENTRY      1
 | 
					 | 
				
			||||||
#define UPDATE_VLAN_ENTRY    2
 | 
					 | 
				
			||||||
#define CLEAR_VLAN_ENTRY     3
 | 
					 | 
				
			||||||
#define RESET_VLAN_TABLE     4
 | 
					 | 
				
			||||||
#define ADD_VLAN_ENTRY       5
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
/*
 | 
					/*
 | 
				
			||||||
** MDIO constants.
 | 
					 *   This program is free software; you can redistribute it and/or modify
 | 
				
			||||||
*/
 | 
					 *   it under the terms of the GNU General Public License as published by
 | 
				
			||||||
 | 
					 *   the Free Software Foundation; either version 2 of the License, or
 | 
				
			||||||
 | 
					 *   (at your option) any later version.
 | 
				
			||||||
 | 
					 *
 | 
				
			||||||
 | 
					 *   This program is distributed in the hope that it will be useful,
 | 
				
			||||||
 | 
					 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 | 
				
			||||||
 | 
					 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 | 
				
			||||||
 | 
					 *   GNU General Public License for more details.
 | 
				
			||||||
 | 
					 *
 | 
				
			||||||
 | 
					 *   You should have received a copy of the GNU General Public License
 | 
				
			||||||
 | 
					 *   along with this program; if not, write to the Free Software
 | 
				
			||||||
 | 
					 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 | 
				
			||||||
 | 
					 *
 | 
				
			||||||
 | 
					 *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
 | 
				
			||||||
 | 
					 */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define MDIO_BASE_STATUS_REG                0x1
 | 
					#include <linux/netdevice.h>
 | 
				
			||||||
#define MDIO_BASE_CONTROL_REG               0x0
 | 
					 | 
				
			||||||
#define MDIO_PHY_ID_HIGH_REG                0x2
 | 
					 | 
				
			||||||
#define MDIO_PHY_ID_LOW_REG                 0x3
 | 
					 | 
				
			||||||
#define MDIO_BC_NEGOTIATE                0x0200
 | 
					 | 
				
			||||||
#define MDIO_BC_FULL_DUPLEX_MASK         0x0100
 | 
					 | 
				
			||||||
#define MDIO_BC_AUTO_NEG_MASK            0x1000
 | 
					 | 
				
			||||||
#define MDIO_BC_SPEED_SELECT_MASK        0x2000
 | 
					 | 
				
			||||||
#define MDIO_STATUS_100_FD               0x4000
 | 
					 | 
				
			||||||
#define MDIO_STATUS_100_HD               0x2000
 | 
					 | 
				
			||||||
#define MDIO_STATUS_10_FD                0x1000
 | 
					 | 
				
			||||||
#define MDIO_STATUS_10_HD                0x0800
 | 
					 | 
				
			||||||
#define MDIO_STATUS_SPEED_DUPLEX_MASK	 0x7800
 | 
					 | 
				
			||||||
#define MDIO_ADVERTISMENT_REG               0x4
 | 
					 | 
				
			||||||
#define MDIO_ADVERT_100_FD                0x100
 | 
					 | 
				
			||||||
#define MDIO_ADVERT_100_HD                0x080
 | 
					 | 
				
			||||||
#define MDIO_ADVERT_10_FD                 0x040
 | 
					 | 
				
			||||||
#define MDIO_ADVERT_10_HD                 0x020
 | 
					 | 
				
			||||||
#define MDIO_LINK_UP_MASK                   0x4
 | 
					 | 
				
			||||||
#define MDIO_START                          0x1
 | 
					 | 
				
			||||||
#define MDIO_READ                           0x2
 | 
					 | 
				
			||||||
#define MDIO_WRITE                          0x1
 | 
					 | 
				
			||||||
#define MDIO_PREAMBLE              0xfffffffful
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define PHY_RESET                        0x8000
 | 
					 | 
				
			||||||
#define AUTO_NEGOTIATION_ENABLE          0X1000
 | 
					 | 
				
			||||||
#define AUTO_NEGOTIATION_COMPLETE          0x20
 | 
					 | 
				
			||||||
#define RESTART_AUTO_NEGOTIATION          0X200
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*ETOP_MDIO_CFG MASKS*/
 | 
					 | 
				
			||||||
#define SMRST_MASK 0X2000
 | 
					 | 
				
			||||||
#define PHYA1_MASK 0X1F00
 | 
					 | 
				
			||||||
#define PHYA0_MASK 0XF8
 | 
					 | 
				
			||||||
#define UMM1_MASK  0X4
 | 
					 | 
				
			||||||
#define UMM0_MASK  0X2
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*ETOP_MDIO_ACCESS MASKS*/
 | 
					 | 
				
			||||||
#define MDIO_RA_MASK    0X80000000
 | 
					 | 
				
			||||||
#define MDIO_RW_MASK    0X40000000
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*ENET_MAC_CFG MASKS*/
 | 
					 | 
				
			||||||
#define BP_MASK     1<<12
 | 
					 | 
				
			||||||
#define CGEN_MASK   1<<11
 | 
					 | 
				
			||||||
#define IFG_MASK    0x3F<<5
 | 
					 | 
				
			||||||
#define IPAUS_MASK  1<<4
 | 
					 | 
				
			||||||
#define EPAUS_MASK  1<<3
 | 
					 | 
				
			||||||
#define DUPLEX_MASK 1<<2
 | 
					 | 
				
			||||||
#define SPEED_MASK  0x2
 | 
					 | 
				
			||||||
#define LINK_MASK   1
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*ENETS_CoS_CFG MASKS*/
 | 
					 | 
				
			||||||
#define VLAN_MASK    2
 | 
					 | 
				
			||||||
#define DSCP_MASK    1
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
/*ENET_CFG MASKS*/
 | 
					 | 
				
			||||||
#define VL2_MASK     1<<29
 | 
					 | 
				
			||||||
#define FTUC_MASK    1<<25
 | 
					 | 
				
			||||||
#define DPBC_MASK    1<<24
 | 
					 | 
				
			||||||
#define DPMC_MASK    1<<23
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define PHY0_ADDR    0
 | 
					 | 
				
			||||||
#define PHY1_ADDR    1
 | 
					 | 
				
			||||||
#define P1M          0
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define OK 0;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
 | 
					 | 
				
			||||||
typedef struct mac_table_entry{
 | 
					 | 
				
			||||||
   u64 mac_address:48;
 | 
					 | 
				
			||||||
   u64 p0:1;
 | 
					 | 
				
			||||||
   u64 p1:1;
 | 
					 | 
				
			||||||
   u64 p2:1;
 | 
					 | 
				
			||||||
   u64 cr:1;
 | 
					 | 
				
			||||||
   u64 ma_st:3;
 | 
					 | 
				
			||||||
   u64 res:9;
 | 
					 | 
				
			||||||
}_mac_table_entry;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct IFX_Switch_VLanTableEntry{
 | 
					 | 
				
			||||||
    u32 vlan_id:12;
 | 
					 | 
				
			||||||
    u32 mp0:1;
 | 
					 | 
				
			||||||
    u32 mp1:1;
 | 
					 | 
				
			||||||
    u32 mp2:1;
 | 
					 | 
				
			||||||
    u32 v:1;
 | 
					 | 
				
			||||||
    u32 res:16;
 | 
					 | 
				
			||||||
}_IFX_Switch_VLanTableEntry;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct mac_table_req{
 | 
					 | 
				
			||||||
    int cmd;
 | 
					 | 
				
			||||||
    int index;
 | 
					 | 
				
			||||||
    u32 data;
 | 
					 | 
				
			||||||
    u64 entry_value;
 | 
					 | 
				
			||||||
}_mac_table_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#else //not CONFIG_CPU_LITTLE_ENDIAN
 | 
					 | 
				
			||||||
typedef struct mac_table_entry{
 | 
					 | 
				
			||||||
   u64 mac_address:48;
 | 
					 | 
				
			||||||
   u64 p0:1;
 | 
					 | 
				
			||||||
   u64 p1:1;
 | 
					 | 
				
			||||||
   u64 p2:1;
 | 
					 | 
				
			||||||
   u64 cr:1;
 | 
					 | 
				
			||||||
   u64 ma_st:3;
 | 
					 | 
				
			||||||
   u64 res:9;
 | 
					 | 
				
			||||||
}_mac_table_entry;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct IFX_Switch_VLanTableEntry{
 | 
					 | 
				
			||||||
    u32 vlan_id:12;
 | 
					 | 
				
			||||||
    u32 mp0:1;
 | 
					 | 
				
			||||||
    u32 mp1:1;
 | 
					 | 
				
			||||||
    u32 mp2:1;
 | 
					 | 
				
			||||||
    u32 v:1;
 | 
					 | 
				
			||||||
    u32 res:16;
 | 
					 | 
				
			||||||
}_IFX_Switch_VLanTableEntry;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct mac_table_req{
 | 
					 | 
				
			||||||
    int cmd;
 | 
					 | 
				
			||||||
    int index;
 | 
					 | 
				
			||||||
    u32 data;
 | 
					 | 
				
			||||||
    u64 entry_value;
 | 
					 | 
				
			||||||
}_mac_table_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#endif //CONFIG_CPU_LITTLE_ENDIAN
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct vlan_cos_req{
 | 
					 | 
				
			||||||
    int pri;
 | 
					 | 
				
			||||||
    int cos_value;
 | 
					 | 
				
			||||||
}_vlan_cos_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct dscp_cos_req{
 | 
					 | 
				
			||||||
    int dscp;
 | 
					 | 
				
			||||||
    int cos_value;
 | 
					 | 
				
			||||||
}_dscp_cos_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct vlan_req{
 | 
					 | 
				
			||||||
    int cmd;
 | 
					 | 
				
			||||||
    int index;
 | 
					 | 
				
			||||||
    u32 data;
 | 
					 | 
				
			||||||
    u32 entry_value;
 | 
					 | 
				
			||||||
}_vlan_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
typedef struct data_req{
 | 
					 | 
				
			||||||
    int index;
 | 
					 | 
				
			||||||
    u32 value;
 | 
					 | 
				
			||||||
}_data_req;
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
enum duplex
 | 
					 | 
				
			||||||
{
 | 
					 | 
				
			||||||
   half,
 | 
					 | 
				
			||||||
   full,
 | 
					 | 
				
			||||||
   autoneg
 | 
					 | 
				
			||||||
};
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
struct ifxmips_mii_priv {
 | 
					struct ifxmips_mii_priv {
 | 
				
			||||||
    struct net_device_stats stats;
 | 
					    struct net_device_stats stats;
 | 
				
			||||||
    int rx_packetlen;
 | 
					 | 
				
			||||||
    u8 *rx_packetdata;
 | 
					 | 
				
			||||||
    int rx_status;
 | 
					 | 
				
			||||||
    int tx_packetlen;
 | 
					 | 
				
			||||||
#ifdef CONFIG_NET_HW_FLOWCONTROL
 | 
					 | 
				
			||||||
    int fc_bit;
 | 
					 | 
				
			||||||
#endif //CONFIG_NET_HW_FLOWCONTROL
 | 
					 | 
				
			||||||
    u8 *tx_packetdata;
 | 
					 | 
				
			||||||
    int tx_status;
 | 
					 | 
				
			||||||
    struct dma_device_info *dma_device;
 | 
					    struct dma_device_info *dma_device;
 | 
				
			||||||
    struct sk_buff *skb;
 | 
					    struct sk_buff *skb;
 | 
				
			||||||
    spinlock_t lock;
 | 
					 | 
				
			||||||
    int mdio_phy_addr;
 | 
					 | 
				
			||||||
    int current_speed;
 | 
					 | 
				
			||||||
    int current_speed_selection;
 | 
					 | 
				
			||||||
    int rx_queue_len;
 | 
					 | 
				
			||||||
    int full_duplex;
 | 
					 | 
				
			||||||
    enum duplex current_duplex;
 | 
					 | 
				
			||||||
};
 | 
					};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif //IFXMIPS_SW_H
 | 
					struct ifxmips_mac {
 | 
				
			||||||
 | 
						unsigned char mac[6];
 | 
				
			||||||
 | 
					};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 
 | 
				
			|||||||
		Reference in New Issue
	
	Block a user