ralink: add support for the mt7530 eval board

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 38345
This commit is contained in:
John Crispin
2013-10-08 21:10:15 +00:00
parent 697bb191b0
commit e382d2c7e6
5 changed files with 177 additions and 40 deletions

View File

@@ -47,7 +47,7 @@
pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "mdio", "i2c", "uartf";
ralink,group = "i2c", "uartf";
ralink,function = "gpio";
};
};
@@ -56,16 +56,19 @@
ethernet@10100000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
ralink,port-map = "llllw";
port@4 {
compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
reg = <4>;
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
port@5 {
compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
reg = <5>;
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
@@ -87,9 +90,6 @@
gsw@10110000 {
ralink,port4 = "gmac";
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
};
sdhci@10130000 {

View File

@@ -0,0 +1,107 @@
/dts-v1/;
/include/ "mt7620a.dtsi"
/ {
compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
model = "Ralink MT7620a + MT7530 evaluation board";
palmbus@10000000 {
spi@b00 {
status = "okay";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fl064k";
reg = <0 0>;
linux,modalias = "m25p80", "s25fl064k";
spi-max-frequency = <10000000>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
label = "firmware";
reg = <0x50000 0x7b0000>;
};
};
};
};
pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "i2c", "uartf";
ralink,function = "gpio";
};
};
};
ethernet@10100000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
ralink,port-map = "llllw";
port@5 {
status = "okay";
ralink,fixed-link = <1000 1 1 1>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
phy1f: ethernet-phy@1f {
reg = <0x1f>;
phy-mode = "rgmii";
};
};
};
gsw@10110000 {
ralink,port4 = "gmac";
};
pcie@10140000 {
status = "okay";
};
};

View File

@@ -298,13 +298,13 @@
};
};
rgmii1_pins: rgmii1 {
mdio {
rgmii1 {
ralink,group = "rgmii1";
ralink,function = "rgmii1";
};
};
rgmii2_pins: rgmii2 {
mdio {
rgmii2 {
ralink,group = "rgmii2";
ralink,function = "rgmii2";
};
@@ -333,14 +333,28 @@
interrupt-parent = <&cpuintc>;
interrupts = <5>;
resets = <&rstctrl 21 &rstctrl 23>;
reset-names = "fe", "esw";
port@4 {
compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
reg = <4>;
status = "disabled";
};
port@5 {
compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
reg = <5>;
status = "disabled";
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
};
};