atheros: shorten lines
Wrap lines over 80 chars or make them shorter by other ways. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41095
This commit is contained in:
Felix Fietkau
@@ -32,7 +32,7 @@
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+obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
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--- /dev/null
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+++ b/drivers/net/ethernet/ar231x/ar231x.c
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@@ -0,0 +1,1257 @@
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@@ -0,0 +1,1254 @@
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+/*
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+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
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+ *
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@@ -159,7 +159,8 @@
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+#define VLAN_HDR 0
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+#endif
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+
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+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
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+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
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+ RX_OFFSET)
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+
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+#ifdef MODULE
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+MODULE_LICENSE("GPL");
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@@ -177,7 +178,8 @@
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+static void ar231x_tx_timeout(struct net_device *dev);
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+
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+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
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+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
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+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
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+ u16 value);
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+static int ar231x_mdiobus_reset(struct mii_bus *bus);
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+static int ar231x_mdiobus_probe(struct net_device *dev);
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+static void ar231x_adjust_link(struct net_device *dev);
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@@ -254,8 +256,8 @@
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+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
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+ tasklet_disable(&sp->rx_tasklet);
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+
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+ sp->eth_regs =
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+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
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+ sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base),
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+ sizeof(*sp->eth_regs));
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+ if (!sp->eth_regs) {
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+ printk("Can't remap eth registers\n");
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+ return -ENXIO;
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@@ -308,10 +310,8 @@
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+ return -1;
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+ }
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+
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+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
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+ dev->name, sp->name,
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+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
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+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
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+ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
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+ dev->irq);
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+
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+ sp->mii_bus = mdiobus_alloc();
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+ if (sp->mii_bus == NULL)
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@@ -442,8 +442,7 @@
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+ return 0;
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+ }
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+
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+ size =
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+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
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+ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
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+ space = kmalloc(size, GFP_KERNEL);
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+ if (space == NULL)
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+ return 1;
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@@ -468,9 +467,7 @@
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+ td->status = 0;
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+ td->devcs = DMA_TX1_CHAINED;
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+ td->addr = 0;
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+ td->descr =
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+ virt_to_phys(&sp->
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+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
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+ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
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+ }
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+
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+ return 0;
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@@ -571,11 +568,14 @@
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+ u16 reg;
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+
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+ sp->link = 1;
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+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
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+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
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+ MII_BMCR);
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+ if (reg & BMCR_ANENABLE) {
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+ /* auto neg enabled */
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+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
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+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
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+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
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+ MII_LPA);
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+ duplex = reg & (LPA_100FULL | LPA_10FULL) ?
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+ 1 : 0;
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+ } else {
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+ /* no auto neg, just read duplex config */
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+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
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@@ -587,13 +587,13 @@
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+ if (duplex) {
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+ /* full duplex */
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+ sp->eth_regs->mac_control =
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+ ((sp->eth_regs->
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+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
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+ (sp->eth_regs->mac_control |
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+ MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
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+ } else {
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+ /* half duplex */
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+ sp->eth_regs->mac_control =
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+ ((sp->eth_regs->
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+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
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+ (sp->eth_regs->mac_control |
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+ MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
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+ }
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+ } else {
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+ /* no link */
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@@ -624,10 +624,9 @@
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+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
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+
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+ /* enable interrupts */
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+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
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+ DMA_STATUS_NIS |
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+ DMA_STATUS_RI |
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+ DMA_STATUS_TI | DMA_STATUS_FBE);
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+ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
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+ DMA_STATUS_RI | DMA_STATUS_TI |
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+ DMA_STATUS_FBE;
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+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
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+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
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+ sp->dma_regs->control =
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@@ -648,13 +647,13 @@
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+ sp->eth_regs->mac_control = flags;
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+
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+ /* Set all Ethernet station address registers to their initial values */
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+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
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+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
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+
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+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
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+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
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+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
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+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
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+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
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+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
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+
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+ sp->eth_regs->mac_addr[0] = ethsah;
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+ sp->eth_regs->mac_addr[1] = ethsal;
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@@ -787,9 +786,7 @@
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+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
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+ DMA_RX1_CHAINED);
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+ rd->addr = virt_to_phys(skb->data);
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+ rd->descr =
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+ virt_to_phys(&sp->
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+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
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+ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
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+ rd->status = DMA_RX_OWN;
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+
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+ idx = DSC_NEXT(idx);
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@@ -849,12 +846,13 @@
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+
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+ } else {
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+ /* alloc new buffer. */
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+ skb_new = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
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+ skb_new = netdev_alloc_skb_ip_align(dev,
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+ AR2313_BUFSIZE);
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+ if (skb_new != NULL) {
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+ skb = sp->rx_skb[idx];
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+ /* set skb */
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+ skb_put(skb,
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+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
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+ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
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+ 0x3fff) - CRC_LEN);
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+
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+ dev->stats.rx_bytes += skb->len;
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+ skb->protocol = eth_type_trans(skb, dev);
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@@ -905,8 +903,8 @@
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+ }
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+ /* done with this descriptor */
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+ dma_unmap_single(NULL, txdesc->addr,
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+ txdesc->devcs & DMA_TX1_BSIZE_MASK,
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+ DMA_TO_DEVICE);
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+ txdesc->devcs & DMA_TX1_BSIZE_MASK,
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+ DMA_TO_DEVICE);
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+ txdesc->status = 0;
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+
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+ if (status & DMA_TX_ERROR) {
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@@ -918,9 +916,8 @@
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+ dev->stats.tx_heartbeat_errors++;
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+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
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+ dev->stats.tx_carrier_errors++;
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+ if (status & (DMA_TX_ERR_LATE |
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+ DMA_TX_ERR_COL |
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+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
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+ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
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+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
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+ dev->stats.tx_aborted_errors++;
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+ } else {
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+ /* transmit OK */
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@@ -1009,13 +1006,13 @@
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+ unsigned int ethsal, ethsah;
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+
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+ /* reset the hardware, in case the MAC address changed */
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+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
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+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
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+
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+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
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+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
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+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
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+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
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+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
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+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
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+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
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+
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+ sp->eth_regs->mac_addr[0] = ethsah;
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+ sp->eth_regs->mac_addr[1] = ethsal;
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@@ -1049,7 +1046,7 @@
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+
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+ /* kill the MAC */
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+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
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+ MAC_CONTROL_TE); /* disable Transmits */
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+ MAC_CONTROL_TE); /* disable Transmits */
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+ /* stop dma */
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+ sp->dma_regs->control = 0;
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+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
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@@ -1260,8 +1257,8 @@
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+ BUG_ON(!phydev);
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+ BUG_ON(phydev->attached_dev);
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+
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+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
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+ PHY_INTERFACE_MODE_MII);
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+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
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+ 0, PHY_INTERFACE_MODE_MII);
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+
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+ if (IS_ERR(phydev)) {
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+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
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@@ -1400,13 +1397,13 @@
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+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
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+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
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+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
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+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
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+#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
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+#define MAC_CONTROL_PM BIT(19) /* pass multicast */
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+#define MAC_CONTROL_F BIT(20) /* full-duplex */
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+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
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+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
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+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
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+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
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+#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
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+
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+#define MII_ADDR_BUSY BIT(0)
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+#define MII_ADDR_WRITE BIT(1)
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@@ -1549,7 +1546,7 @@
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+
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+
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+ struct timer_list link_timer;
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+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
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+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
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+ unsigned short mac;
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+ unsigned short link; /* 0 - link down, 1 - link up */
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+ u16 phy_data;
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