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ramips: fix some clocks in mt7621.dtsi

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As the cpu clock calculation has been fixed, the clock for gic and spi
should be also fixed.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
This commit is contained in:
Weijie Gao
2018-11-19 00:07:01 +08:00
committed by John Crispin
parent c7ca224299
commit ed25e3ac02
1 changed files with 2 additions and 11 deletions
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13
target/linux/ramips/dts/mt7621.dtsi
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@@ -41,14 +41,6 @@
clock-output-names = "cpu", "bus";
};
cpuclock: cpuclock {
#clock-cells = <0>;
compatible = "fixed-clock";
/* FIXME: there should be way to detect this */
clock-frequency = <880000000>;
};
sysclock: sysclock {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -176,7 +168,6 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysclock>;
clock-frequency = <50000000>;
interrupt-parent = <&gic>;
@@ -193,7 +184,7 @@
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
clocks = <&sysclock>;
clocks = <&pll MT7621_CLK_BUS>;
resets = <&rstctrl 18>;
reset-names = "spi";
@@ -402,7 +393,7 @@
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpuclock>;
clocks = <&pll MT7621_CLK_CPU>;
};
};