oxnas: add SoC restart driver for reboot
Refresh oxnas kernel config while at it.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(commit c1a8054114 "oxnas: add SoC restart driver for reboot" on master)
This commit is contained in:
Daniel Golle
@@ -12,6 +12,11 @@ CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_CPU_AUTO=y
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# CONFIG_ARCH_MULTI_V4 is not set
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# CONFIG_ARCH_MULTI_V4T is not set
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CONFIG_ARCH_MULTI_V4_V5=y
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CONFIG_ARCH_MULTI_V5=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
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@@ -25,13 +30,13 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARCH_WANT_LIBATA_LEDS=y
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CONFIG_ARM=y
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
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# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
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CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_CPU_SUSPEND=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_L1_CACHE_SHIFT=5
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@@ -43,7 +48,6 @@ CONFIG_ARM_TIMER_SP804=y
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CONFIG_ARM_UNWIND=y
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CONFIG_ATAGS=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BINARY_PRINTF=y
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CONFIG_BLK_CMDLINE_PARSER=y
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CONFIG_BLK_DEBUG_FS=y
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CONFIG_BLK_DEV_BSG=y
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@@ -51,9 +55,9 @@ CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=16
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CONFIG_BLK_DEV_RAM_SIZE=65536
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_SCSI_REQUEST=y
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# CONFIG_BPF_SYSCALL is not set
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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@@ -72,16 +76,34 @@ CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_OXNAS=y
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CONFIG_COMPAT_BRK=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTEXT_SWITCH_TRACER=y
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CONFIG_COREDUMP=y
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CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
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CONFIG_CPU_32v5=y
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CONFIG_CPU_ABRT_EV5TJ=y
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CONFIG_CPU_ARM926T=y
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# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
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CONFIG_CPU_CACHE_VIVT=y
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CONFIG_CPU_COPY_V4WB=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_LEGACY=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V4WBI=y
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CONFIG_CPU_USE_DOMAINS=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_DEBUG_ALIGN_RODATA=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_UART_8250 is not set
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# CONFIG_DEBUG_USER is not set
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CONFIG_DECOMPRESS_BZIP2=y
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CONFIG_DECOMPRESS_GZIP=y
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@@ -98,17 +120,19 @@ CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMA_CMA=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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# CONFIG_DWMAC_DWC_QOS_ETH is not set
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_OXNAS=y
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CONFIG_EARLY_PRINTK=y
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# CONFIG_EDAC_SUPPORT is not set
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_ELF_CORE=y
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CONFIG_FAT_FS=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FREEZER=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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@@ -117,15 +141,12 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GLOB=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_GENERIC=y
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@@ -160,7 +181,6 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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@@ -197,11 +217,9 @@ CONFIG_IOMMU_SUPPORT=y
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CONFIG_IOSCHED_CFQ=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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# CONFIG_ISDN is not set
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CONFIG_JBD2=y
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# CONFIG_JFFS2_FS is not set
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CONFIG_KALLSYMS=y
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CONFIG_KERNEL_GZIP=y
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@@ -220,35 +238,34 @@ CONFIG_LEGACY_PTY_COUNT=256
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CONFIG_LIBFDT=y
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CONFIG_LOCALVERSION_AUTO=y
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CONFIG_LZ4_DECOMPRESS=y
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CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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# CONFIG_MACH_OX810SE is not set
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MEMORY_ISOLATION=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MIGRATION=y
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CONFIG_MODULES_TREE_LOOKUP=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_KUSER_HELPERS=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_PTP_CLASSIFY=y
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CONFIG_NLS=y
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CONFIG_NOP_TRACER=y
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CONFIG_NO_BOOTMEM=y
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CONFIG_NO_HZ=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS_PCI=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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CONFIG_OF_RESERVED_MEM=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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@@ -257,6 +274,8 @@ CONFIG_PAGE_OFFSET=0xC0000000
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# CONFIG_PANIC_ON_OOPS is not set
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CONFIG_PANIC_ON_OOPS_VALUE=0
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CONFIG_PANIC_TIMEOUT=0
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# CONFIG_PCI_DOMAINS_GENERIC is not set
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# CONFIG_PCI_SYSCALL is not set
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CONFIG_PERF_EVENTS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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@@ -268,11 +287,14 @@ CONFIG_PM=y
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CONFIG_PM_CLK=y
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# CONFIG_PM_DEBUG is not set
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CONFIG_PM_SLEEP=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_OXNAS=y
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CONFIG_PPS=y
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CONFIG_PROBE_EVENTS=y
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CONFIG_PTP_1588_CLOCK=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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# CONFIG_RCU_NEED_SEGCBLIST is not set
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_RCU_TRACE=y
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CONFIG_RD_BZIP2=y
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CONFIG_RD_GZIP=y
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@@ -285,7 +307,6 @@ CONFIG_REGMAP=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RESET_OXNAS=y
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CONFIG_RING_BUFFER=y
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CONFIG_RWSEM_XCHGADD_ALGORITHM=y
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CONFIG_SCHED_DEBUG=y
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# CONFIG_SCHED_INFO is not set
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@@ -302,6 +323,7 @@ CONFIG_SIMPLE_PM_BUS=y
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CONFIG_SLUB_DEBUG=y
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CONFIG_SOCK_DIAG=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPLIT_PTLOCK_CPUS=999999
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CONFIG_SRCU=y
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CONFIG_STACKTRACE=y
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# CONFIG_STAGING is not set
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@@ -316,10 +338,10 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TIMER_OF=y
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CONFIG_TIMER_PROBE=y
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CONFIG_TINY_SRCU=y
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CONFIG_TRACE_CLOCK=y
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CONFIG_UEVENT_HELPER_PATH=""
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CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
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CONFIG_UPROBES=y
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CONFIG_UPROBE_EVENTS=y
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CONFIG_USB_SUPPORT=y
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# CONFIG_USERIO is not set
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CONFIG_USE_OF=y
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@@ -344,5 +366,4 @@ CONFIG_XZ_DEC_SPARC=y
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CONFIG_XZ_DEC_X86=y
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CONFIG_ZBOOT_ROM_BSS=0
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CONFIG_ZBOOT_ROM_TEXT=0
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CONFIG_ZLIB_DEFLATE=y
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CONFIG_ZLIB_INFLATE=y
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229
target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c
Normal file
229
target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c
Normal file
@@ -0,0 +1,229 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* oxnas SoC reset driver
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* based on:
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* Microsemi MIPS SoC reset driver
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* and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
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*
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* License: GPL
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* Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/notifier.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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/* bit numbers of reset control register */
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#define SYS_CTRL_RST_SCU 0
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#define SYS_CTRL_RST_COPRO 1
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#define SYS_CTRL_RST_ARM0 2
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#define SYS_CTRL_RST_ARM1 3
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#define SYS_CTRL_RST_USBHS 4
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#define SYS_CTRL_RST_USBHSPHYA 5
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#define SYS_CTRL_RST_MACA 6
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#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
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#define SYS_CTRL_RST_PCIEA 7
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#define SYS_CTRL_RST_SGDMA 8
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#define SYS_CTRL_RST_CIPHER 9
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#define SYS_CTRL_RST_DDR 10
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#define SYS_CTRL_RST_SATA 11
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#define SYS_CTRL_RST_SATA_LINK 12
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#define SYS_CTRL_RST_SATA_PHY 13
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#define SYS_CTRL_RST_PCIEPHY 14
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#define SYS_CTRL_RST_STATIC 15
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#define SYS_CTRL_RST_GPIO 16
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#define SYS_CTRL_RST_UART1 17
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#define SYS_CTRL_RST_UART2 18
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#define SYS_CTRL_RST_MISC 19
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#define SYS_CTRL_RST_I2S 20
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#define SYS_CTRL_RST_SD 21
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#define SYS_CTRL_RST_MACB 22
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#define SYS_CTRL_RST_PCIEB 23
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#define SYS_CTRL_RST_VIDEO 24
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#define SYS_CTRL_RST_DDR_PHY 25
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#define SYS_CTRL_RST_USBHSPHYB 26
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#define SYS_CTRL_RST_USBDEV 27
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#define SYS_CTRL_RST_ARMDBG 29
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#define SYS_CTRL_RST_PLLA 30
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#define SYS_CTRL_RST_PLLB 31
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/* bit numbers of clock control register */
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#define SYS_CTRL_CLK_COPRO 0
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#define SYS_CTRL_CLK_DMA 1
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#define SYS_CTRL_CLK_CIPHER 2
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#define SYS_CTRL_CLK_SD 3
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#define SYS_CTRL_CLK_SATA 4
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#define SYS_CTRL_CLK_I2S 5
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#define SYS_CTRL_CLK_USBHS 6
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#define SYS_CTRL_CLK_MACA 7
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#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
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#define SYS_CTRL_CLK_PCIEA 8
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#define SYS_CTRL_CLK_STATIC 9
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#define SYS_CTRL_CLK_MACB 10
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#define SYS_CTRL_CLK_PCIEB 11
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#define SYS_CTRL_CLK_REF600 12
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#define SYS_CTRL_CLK_USBDEV 13
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#define SYS_CTRL_CLK_DDR 14
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#define SYS_CTRL_CLK_DDRPHY 15
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#define SYS_CTRL_CLK_DDRCK 16
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/* Regmap offsets */
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#define CLK_SET_REGOFFSET 0x2c
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#define CLK_CLR_REGOFFSET 0x30
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#define RST_SET_REGOFFSET 0x34
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#define RST_CLR_REGOFFSET 0x38
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#define SECONDARY_SEL_REGOFFSET 0x14
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#define TERTIARY_SEL_REGOFFSET 0x8c
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#define QUATERNARY_SEL_REGOFFSET 0x94
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#define DEBUG_SEL_REGOFFSET 0x9c
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#define ALTERNATIVE_SEL_REGOFFSET 0xa4
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#define PULLUP_SEL_REGOFFSET 0xac
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#define SEC_SECONDARY_SEL_REGOFFSET 0x100014
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#define SEC_TERTIARY_SEL_REGOFFSET 0x10008c
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#define SEC_QUATERNARY_SEL_REGOFFSET 0x100094
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#define SEC_DEBUG_SEL_REGOFFSET 0x10009c
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#define SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
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#define SEC_PULLUP_SEL_REGOFFSET 0x1000ac
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|
||||
|
||||
struct oxnas_restart_context {
|
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struct regmap *sys_ctrl;
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struct notifier_block restart_handler;
|
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};
|
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|
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static int oxnas_restart_handle(struct notifier_block *this,
|
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unsigned long mode, void *cmd)
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{
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struct oxnas_restart_context *ctx = container_of(this, struct
|
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oxnas_restart_context,
|
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restart_handler);
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u32 value;
|
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|
||||
/* Assert reset to cores as per power on defaults
|
||||
* Don't touch the DDR interface as things will come to an impromptu stop
|
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* NB Possibly should be asserting reset for PLLB, but there are timing
|
||||
* concerns here according to the docs */
|
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value = BIT(SYS_CTRL_RST_COPRO) |
|
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BIT(SYS_CTRL_RST_USBHS) |
|
||||
BIT(SYS_CTRL_RST_USBHSPHYA) |
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||||
BIT(SYS_CTRL_RST_MACA) |
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BIT(SYS_CTRL_RST_PCIEA) |
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BIT(SYS_CTRL_RST_SGDMA) |
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BIT(SYS_CTRL_RST_CIPHER) |
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||||
BIT(SYS_CTRL_RST_SATA) |
|
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BIT(SYS_CTRL_RST_SATA_LINK) |
|
||||
BIT(SYS_CTRL_RST_SATA_PHY) |
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||||
BIT(SYS_CTRL_RST_PCIEPHY) |
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||||
BIT(SYS_CTRL_RST_STATIC) |
|
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BIT(SYS_CTRL_RST_UART1) |
|
||||
BIT(SYS_CTRL_RST_UART2) |
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BIT(SYS_CTRL_RST_MISC) |
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BIT(SYS_CTRL_RST_I2S) |
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BIT(SYS_CTRL_RST_SD) |
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BIT(SYS_CTRL_RST_MACB) |
|
||||
BIT(SYS_CTRL_RST_PCIEB) |
|
||||
BIT(SYS_CTRL_RST_VIDEO) |
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||||
BIT(SYS_CTRL_RST_USBHSPHYB) |
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||||
BIT(SYS_CTRL_RST_USBDEV);
|
||||
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regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
|
||||
|
||||
/* Release reset to cores as per power on defaults */
|
||||
regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(SYS_CTRL_RST_GPIO));
|
||||
|
||||
/* Disable clocks to cores as per power-on defaults - must leave DDR
|
||||
* related clocks enabled otherwise we'll stop rather abruptly. */
|
||||
value =
|
||||
BIT(SYS_CTRL_CLK_COPRO) |
|
||||
BIT(SYS_CTRL_CLK_DMA) |
|
||||
BIT(SYS_CTRL_CLK_CIPHER) |
|
||||
BIT(SYS_CTRL_CLK_SD) |
|
||||
BIT(SYS_CTRL_CLK_SATA) |
|
||||
BIT(SYS_CTRL_CLK_I2S) |
|
||||
BIT(SYS_CTRL_CLK_USBHS) |
|
||||
BIT(SYS_CTRL_CLK_MAC) |
|
||||
BIT(SYS_CTRL_CLK_PCIEA) |
|
||||
BIT(SYS_CTRL_CLK_STATIC) |
|
||||
BIT(SYS_CTRL_CLK_MACB) |
|
||||
BIT(SYS_CTRL_CLK_PCIEB) |
|
||||
BIT(SYS_CTRL_CLK_REF600) |
|
||||
BIT(SYS_CTRL_CLK_USBDEV);
|
||||
|
||||
regmap_write(ctx->sys_ctrl, CLK_CLR_REGOFFSET, value);
|
||||
|
||||
/* Enable clocks to cores as per power-on defaults */
|
||||
|
||||
/* Set sys-control pin mux'ing as per power-on defaults */
|
||||
regmap_write(ctx->sys_ctrl, SECONDARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, TERTIARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, QUATERNARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, DEBUG_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, ALTERNATIVE_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, PULLUP_SEL_REGOFFSET, 0);
|
||||
|
||||
regmap_write(ctx->sys_ctrl, SEC_SECONDARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, SEC_TERTIARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, SEC_QUATERNARY_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, SEC_DEBUG_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
|
||||
regmap_write(ctx->sys_ctrl, SEC_PULLUP_SEL_REGOFFSET, 0);
|
||||
|
||||
/* No need to save any state, as the ROM loader can determine whether
|
||||
* reset is due to power cycling or programatic action, just hit the
|
||||
* (self-clearing) CPU reset bit of the block reset register */
|
||||
value =
|
||||
BIT(SYS_CTRL_RST_SCU) |
|
||||
BIT(SYS_CTRL_RST_ARM0) |
|
||||
BIT(SYS_CTRL_RST_ARM1);
|
||||
|
||||
regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
|
||||
|
||||
pr_emerg("Unable to restart system\n");
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static int oxnas_restart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct oxnas_restart_context *ctx;
|
||||
struct regmap *sys_ctrl;
|
||||
struct device *dev = &pdev->dev;
|
||||
int err = 0;
|
||||
|
||||
sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
|
||||
if (IS_ERR(sys_ctrl))
|
||||
return PTR_ERR(sys_ctrl);
|
||||
|
||||
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
ctx->sys_ctrl = sys_ctrl;
|
||||
ctx->restart_handler.notifier_call = oxnas_restart_handle;
|
||||
ctx->restart_handler.priority = 192;
|
||||
err = register_restart_handler(&ctx->restart_handler);
|
||||
if (err)
|
||||
dev_err(dev, "can't register restart notifier (err=%d)\n", err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct of_device_id oxnas_restart_of_match[] = {
|
||||
{ .compatible = "oxsemi,ox820-sys-ctrl" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver oxnas_restart_driver = {
|
||||
.probe = oxnas_restart_probe,
|
||||
.driver = {
|
||||
.name = "oxnas-chip-reset",
|
||||
.of_match_table = oxnas_restart_of_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(oxnas_restart_driver);
|
||||
25
target/linux/oxnas/patches-4.14/150-oxnas-restart.patch
Normal file
25
target/linux/oxnas/patches-4.14/150-oxnas-restart.patch
Normal file
@@ -0,0 +1,25 @@
|
||||
--- a/drivers/power/reset/Kconfig
|
||||
+++ b/drivers/power/reset/Kconfig
|
||||
@@ -113,6 +113,12 @@ config POWER_RESET_MSM
|
||||
help
|
||||
Power off and restart support for Qualcomm boards.
|
||||
|
||||
+config POWER_RESET_OXNAS
|
||||
+ bool "OXNAS SoC restart driver"
|
||||
+ depends on ARCH_OXNAS
|
||||
+ help
|
||||
+ Restart support for OXNAS boards.
|
||||
+
|
||||
config POWER_RESET_PIIX4_POWEROFF
|
||||
tristate "Intel PIIX4 power-off driver"
|
||||
depends on PCI
|
||||
--- a/drivers/power/reset/Makefile
|
||||
+++ b/drivers/power/reset/Makefile
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) +
|
||||
obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
|
||||
obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
|
||||
+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
|
||||
obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
|
||||
Reference in New Issue
Block a user