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ath79: fix eth0 PLL registers on WD My Net Wi-Fi Range Extender

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This replaces the register bits for RGMII delay on the MAC side in favor
of having the RGMII delay on the PHY side by setting the phy-mode
property to rgmii-id (RGMII internal delay), which is supported by the
at803x driver.  Speed 1000 is fixed as a result, so now all ethernet
speeds function.

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Michael Pratt <mcpratt@pm.me>
This commit is contained in:
Jonathan A. Kollasch
2020-09-11 14:33:39 -05:00
committed by Adrian Schmutzler
parent 3e0387b3db
commit f36990eae7
1 changed files with 2 additions and 2 deletions
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4
target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
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@@ -144,10 +144,10 @@
&eth0 {
status = "okay";
pll-data = <0x0e000000 0x3c000101 0x3c001313>;
pll-data = <0x02000000 0x00000101 0x00001313>;
/* ethernet MAC is stored in nvram */
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&phy4>;
gmac-config {