ar71xx: fix QCA955X SGMII link loss
The QCA955X is affected by a hardware bug which causes link-loss of the SGMII link between SoC and PHY. This happens on change of link-state or speed. It is not really known what causes this bug. It definitely occurs when using a AR8033 Gigabit Ethernet PHY. Qualcomm solves this Bug in a similar fashion. We need to apply the fix on a per-device base via platform-data as performing the fixup work will break connectivity in case the SGMII interface is connected to a Switch. This bug was first proposed to be fixed by Sven Eckelmann in 2016. https://patchwork.ozlabs.org/patch/604782/ Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Signed-off-by: David Bauer <mail@david-bauer.net>
This commit is contained in:
David Bauer
committed by
John Crispin
John Crispin
parent
fbe17867da
commit
f4f99ec973
@@ -155,6 +155,7 @@ static void __init fritz450E_setup(void) {
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth0_data.phy_mask = BIT(FRITZ450E_PHY_ADDRESS);
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ath79_eth0_data.enable_sgmii_fixup = 1;
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ath79_eth0_pll_data.pll_1000 = 0x03000000;
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ath79_eth0_pll_data.pll_100 = 0x00000101;
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ath79_eth0_pll_data.pll_10 = 0x00001313;
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@@ -37,6 +37,7 @@ struct ag71xx_platform_data {
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u8 is_ar724x:1;
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u8 has_ar8216:1;
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u8 use_flow_control:1;
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u8 enable_sgmii_fixup:1;
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u8 disable_inline_checksum_engine:1;
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struct ag71xx_switch_platform_data *switch_data;
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@@ -66,6 +66,8 @@
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#define AG71XX_TX_RING_SIZE_MAX 128
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#define AG71XX_RX_RING_SIZE_MAX 256
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#define QCA955X_SGMII_LINK_WAR_MAX_TRY 10
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#ifdef CONFIG_AG71XX_DEBUG
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#define DBG(fmt, args...) pr_debug(fmt, ## args)
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#else
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@@ -31,6 +31,7 @@ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
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#define ETH_SWITCH_HEADER_LEN 2
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static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
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static void ag71xx_qca955x_sgmii_init(void);
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static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
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{
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@@ -610,6 +611,9 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update)
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if (update && pdata->set_speed)
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pdata->set_speed(ag->speed);
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if (update && pdata->enable_sgmii_fixup)
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ag71xx_qca955x_sgmii_init();
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
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ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
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@@ -913,6 +917,81 @@ static void ag71xx_tx_timeout(struct net_device *dev)
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schedule_delayed_work(&ag->restart_work, 1);
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}
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static void ag71xx_bit_set(void __iomem *reg, u32 bit)
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{
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u32 val = __raw_readl(reg) | bit;
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__raw_writel(val, reg);
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__raw_readl(reg);
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}
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static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
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{
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u32 val = __raw_readl(reg) & ~bit;
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__raw_writel(val, reg);
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__raw_readl(reg);
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}
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static void ag71xx_qca955x_sgmii_init()
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{
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void __iomem *gmac_base;
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u32 mr_an_status, sgmii_status;
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u8 tries = 0;
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gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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if (!gmac_base)
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goto sgmii_out;
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mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
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if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
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goto sgmii_out;
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__raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET ,
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gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
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__raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
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udelay(10);
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/* Init sequence */
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
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QCA955X_SGMII_RESET_HW_RX_125M_N);
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udelay(10);
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
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QCA955X_SGMII_RESET_RX_125M_N);
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udelay(10);
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
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QCA955X_SGMII_RESET_TX_125M_N);
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udelay(10);
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
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QCA955X_SGMII_RESET_RX_CLK_N);
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udelay(10);
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
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QCA955X_SGMII_RESET_TX_CLK_N);
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udelay(10);
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do {
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ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
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QCA955X_MR_AN_CONTROL_PHY_RESET |
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QCA955X_MR_AN_CONTROL_AN_ENABLE);
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udelay(100);
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ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
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QCA955X_MR_AN_CONTROL_PHY_RESET);
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mdelay(10);
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sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF;
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if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) {
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pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n");
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break;
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}
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} while (!(sgmii_status == 0xf || sgmii_status == 0x10));
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sgmii_out:
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iounmap(gmac_base);
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}
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static void ag71xx_restart_work_func(struct work_struct *work)
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{
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struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
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@@ -0,0 +1,44 @@
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Index: linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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===================================================================
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--- linux-4.9.111.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -134,7 +134,7 @@
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#define QCA955X_PCI_CTRL_SIZE 0x100
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#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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-#define QCA955X_GMAC_SIZE 0x40
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+#define QCA955X_GMAC_SIZE 0x64
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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@@ -1269,7 +1269,11 @@
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*/
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#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+#define QCA955X_GMAC_REG_SGMII_RESET 0x14
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#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
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+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
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+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
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+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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@@ -1291,6 +1295,18 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0
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+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
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+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
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+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
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+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
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+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
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+
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+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
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+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
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+
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+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
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+
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#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
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