mediatek: update patches
* fixes NAND * adds latest ethernet patches Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
615
target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi
Normal file
615
target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi
Normal file
@@ -0,0 +1,615 @@
|
||||
/*
|
||||
* Copyright (c) 2016 MediaTek Inc.
|
||||
* Author: John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt2701-clk.h>
|
||||
#include <dt-bindings/power/mt2701-power.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/reset-controller/mt2701-resets.h>
|
||||
#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
|
||||
#include "skeleton64.dtsi"
|
||||
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7623";
|
||||
interrupt-parent = <&sysirq>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "mediatek,mt6589-smp";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points = <
|
||||
598000 1150000
|
||||
747500 1150000
|
||||
1040000 1150000
|
||||
1196000 1200000
|
||||
1300000 1300000
|
||||
>;
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points = <
|
||||
598000 1150000
|
||||
747500 1150000
|
||||
1040000 1150000
|
||||
1196000 1200000
|
||||
1300000 1300000
|
||||
>;
|
||||
};
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points = <
|
||||
598000 1150000
|
||||
747500 1150000
|
||||
1040000 1150000
|
||||
1196000 1200000
|
||||
1300000 1300000
|
||||
>;
|
||||
};
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points = <
|
||||
598000 1150000
|
||||
747500 1150000
|
||||
1040000 1150000
|
||||
1196000 1200000
|
||||
1300000 1300000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
system_clk: dummy13m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc_clk: dummy32k {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk32k";
|
||||
};
|
||||
|
||||
clk26m: dummy26m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clock-frequency = <13000000>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
topckgen: power-controller@10000000 {
|
||||
compatible = "mediatek,mt7623-topckgen",
|
||||
"mediatek,mt2701-topckgen",
|
||||
"syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
infracfg: power-controller@10001000 {
|
||||
compatible = "mediatek,mt7623-infracfg",
|
||||
"mediatek,mt2701-infracfg",
|
||||
"syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pericfg: pericfg@10003000 {
|
||||
compatible = "mediatek,mt7623-pericfg",
|
||||
"mediatek,mt2701-pericfg",
|
||||
"syscon";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt7623-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
||||
pins-are-numbered;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
syscfg_pctl_a: syscfg@10005000 {
|
||||
compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
scpsys: scpsys@10006000 {
|
||||
#power-domain-cells = <1>;
|
||||
compatible = "mediatek,mt7623-scpsys",
|
||||
"mediatek,mt2701-scpsys";
|
||||
reg = <0 0x10006000 0 0x1000>;
|
||||
infracfg = <&infracfg>;
|
||||
clocks = <&clk26m>,
|
||||
<&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mfg", "mm";
|
||||
};
|
||||
|
||||
watchdog: watchdog@10007000 {
|
||||
compatible = "mediatek,mt7623-wdt",
|
||||
"mediatek,mt6589-wdt";
|
||||
reg = <0 0x10007000 0 0x100>;
|
||||
};
|
||||
|
||||
timer: timer@10008000 {
|
||||
compatible = "mediatek,mt7623-timer",
|
||||
"mediatek,mt6577-timer";
|
||||
reg = <0 0x10008000 0 0x80>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&system_clk>, <&rtc_clk>;
|
||||
clock-names = "system-clk", "rtc-clk";
|
||||
};
|
||||
|
||||
pwrap: pwrap@1000d000 {
|
||||
compatible = "mediatek,mt7623-pwrap",
|
||||
"mediatek,mt2701-pwrap";
|
||||
reg = <0 0x1000d000 0 0x1000>;
|
||||
reg-names = "pwrap";
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
|
||||
reset-names = "pwrap";
|
||||
clocks = <&infracfg CLK_INFRA_PMICSPI>,
|
||||
<&infracfg CLK_INFRA_PMICWRAP>;
|
||||
clock-names = "spi", "wrap";
|
||||
};
|
||||
|
||||
sysirq: interrupt-controller@10200100 {
|
||||
compatible = "mediatek,mt7623-sysirq",
|
||||
"mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10200100 0 0x1c>;
|
||||
};
|
||||
|
||||
apmixedsys: apmixedsys@10209000 {
|
||||
compatible = "mediatek,mt7623-apmixedsys",
|
||||
"mediatek,mt2701-apmixedsys";
|
||||
reg = <0 0x10209000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10211000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10211000 0 0x1000>,
|
||||
<0 0x10212000 0 0x1000>,
|
||||
<0 0x10214000 0 0x2000>,
|
||||
<0 0x10216000 0 0x2000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt7623-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
reg = <0 0x11007000 0 0x70>,
|
||||
<0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C0>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt7623-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
reg = <0 0x11008000 0 0x70>,
|
||||
<0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C1>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11009000 {
|
||||
compatible = "mediatek,mt7623-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
reg = <0 0x11009000 0 0x70>,
|
||||
<0 0x11000300 0 0x80>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C2>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt7623-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_UART0_SEL>,
|
||||
<&pericfg CLK_PERI_UART0>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt7623-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_UART1_SEL>,
|
||||
<&pericfg CLK_PERI_UART1>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt7623-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_UART2_SEL>,
|
||||
<&pericfg CLK_PERI_UART2>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@11005000 {
|
||||
compatible = "mediatek,mt7623-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11005000 0 0x400>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_UART3_SEL>,
|
||||
<&pericfg CLK_PERI_UART3>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@11006000 {
|
||||
compatible = "mediatek,mt7623-pwm";
|
||||
|
||||
reg = <0 0x11006000 0 0x1000>;
|
||||
|
||||
resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
|
||||
reset-names = "pwm";
|
||||
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&pericfg CLK_PERI_PWM>,
|
||||
<&pericfg CLK_PERI_PWM1>,
|
||||
<&pericfg CLK_PERI_PWM2>,
|
||||
<&pericfg CLK_PERI_PWM3>,
|
||||
<&pericfg CLK_PERI_PWM4>,
|
||||
<&pericfg CLK_PERI_PWM5>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2",
|
||||
"pwm3", "pwm4", "pwm5";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@1100a000 {
|
||||
compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
|
||||
reg = <0 0x1100a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_SPI0>;
|
||||
clock-names = "main";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nandc: nfi@1100d000 {
|
||||
compatible = "mediatek,mt2701-nfc";
|
||||
reg = <0 0x1100d000 0 0x1000>;
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_NFI>,
|
||||
<&pericfg CLK_PERI_NFI_PAD>;
|
||||
clock-names = "nfi_clk", "pad_clk";
|
||||
status = "disabled";
|
||||
ecc-engine = <&bch>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
bch: ecc@1100e000 {
|
||||
compatible = "mediatek,mt2701-ecc";
|
||||
reg = <0 0x1100e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
||||
clock-names = "nfiecc_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7623-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
||||
<&topckgen CLK_TOP_MSDC30_0_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@11240000 {
|
||||
compatible = "mediatek,mt7623-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11240000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
||||
<&topckgen CLK_TOP_MSDC30_1_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@1a1c0000 {
|
||||
compatible = "mediatek,mt2701-xhci",
|
||||
"mediatek,mt8173-xhci";
|
||||
reg = <0 0x1a1c0000 0 0x1000>,
|
||||
<0 0x1a1c4700 0 0x0100>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
|
||||
<&topckgen CLK_TOP_ETHIF_SEL>;
|
||||
clock-names = "sys_ck", "ethif";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||
phys = <&phy_port0 PHY_TYPE_USB3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy1: usb-phy@1a1c4000 {
|
||||
compatible = "mediatek,mt2701-u3phy",
|
||||
"mediatek,mt8173-u3phy";
|
||||
reg = <0 0x1a1c4000 0 0x0700>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "u3phya_ref";
|
||||
#phy-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
phy_port0: phy_port0: port@1a1c4800 {
|
||||
reg = <0 0x1a1c4800 0 0x800>;
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb2: usb@1a240000 {
|
||||
compatible = "mediatek,mt2701-xhci",
|
||||
"mediatek,mt8173-xhci";
|
||||
reg = <0 0x1a240000 0 0x1000>,
|
||||
<0 0x1a244700 0 0x0100>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
|
||||
<&topckgen CLK_TOP_ETHIF_SEL>;
|
||||
clock-names = "sys_ck", "ethif";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||
phys = <&u3phy2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy2: usb-phy@1a244000 {
|
||||
compatible = "mediatek,mt2701-u3phy",
|
||||
"mediatek,mt8173-u3phy";
|
||||
reg = <0 0x1a244000 0 0x0700>,
|
||||
<0 0x1a244800 0 0x0800>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "u3phya_ref";
|
||||
#phy-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hifsys: clock-controller@1a000000 {
|
||||
compatible = "mediatek,mt7623-hifsys",
|
||||
"mediatek,mt2701-hifsys",
|
||||
"syscon";
|
||||
reg = <0 0x1a000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pcie: pcie@1a140000 {
|
||||
compatible = "mediatek,mt7623-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
|
||||
<0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
|
||||
<0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
|
||||
<0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
|
||||
reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "pcie0", "pcie1", "pcie2";
|
||||
clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
|
||||
clock-names = "pcie";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
|
||||
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
|
||||
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
|
||||
reset-names = "pcie0", "pcie1", "pcie2";
|
||||
|
||||
mediatek,hifsys = <&hifsys>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
|
||||
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@2,0{
|
||||
device_type = "pci";
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@3,0{
|
||||
device_type = "pci";
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@1b000000 {
|
||||
compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||
reg = <0 0x1b000000 0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
eth: ethernet@1b100000 {
|
||||
compatible = "mediatek,mt7623-eth";
|
||||
reg = <0 0x1b100000 0 0x20000>;
|
||||
|
||||
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||
<ðsys CLK_ETHSYS_ESW>,
|
||||
<ðsys CLK_ETHSYS_GP2>,
|
||||
<ðsys CLK_ETHSYS_GP1>;
|
||||
clock-names = "ethif", "esw", "gp2", "gp1";
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
|
||||
resets = <ðsys 6>;
|
||||
reset-names = "eth";
|
||||
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,pctl = <&syscfg_pctl_a>;
|
||||
|
||||
mediatek,switch = <&gsw>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gmac1: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii-rxid";
|
||||
};
|
||||
|
||||
phy1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw: switch@1b100000 {
|
||||
compatible = "mediatek,mt7623-gsw";
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <168 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <ðsys 2>;
|
||||
reset-names = "eth";
|
||||
clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
|
||||
clock-names = "trgpll";
|
||||
mt7530-supply = <&mt6323_vpa_reg>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -14,11 +14,11 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7623.dtsi"
|
||||
#include "_mt7623.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7623 evaluation board";
|
||||
model = "MediaTek MT7623 NAND evaluation board";
|
||||
compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
||||
|
||||
chosen {
|
||||
@@ -341,6 +341,16 @@
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm {
|
||||
pins_pwm1 {
|
||||
pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
|
||||
};
|
||||
|
||||
pins_pwm2 {
|
||||
pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nandc {
|
||||
@@ -416,6 +426,14 @@
|
||||
&gmac2 {
|
||||
mac-address = [00 11 22 33 44 55];
|
||||
status = "okay";
|
||||
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
&gsw {
|
||||
@@ -424,3 +442,9 @@
|
||||
mediatek,reset-pin = <&pio 15 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7623.dtsi"
|
||||
#include "_mt7623.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
@@ -436,6 +436,16 @@
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm {
|
||||
pins_pwm1 {
|
||||
pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
|
||||
};
|
||||
|
||||
pins_pwm2 {
|
||||
pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
@@ -464,6 +474,7 @@
|
||||
&gmac2 {
|
||||
mac-address = [00 11 22 33 44 55];
|
||||
status = "okay";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
|
||||
&gsw {
|
||||
@@ -472,3 +483,9 @@
|
||||
mediatek,reset-pin = <&pio 15 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user