sync ssb with upstream

SVN-Revision: 9302
This commit is contained in:
Felix Fietkau
2007-10-14 02:47:36 +00:00
parent af03fdb6c5
commit fd811bf54c
37 changed files with 926 additions and 4665 deletions

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@@ -1,14 +1,12 @@
#ifndef LINUX_SSB_H_
#define LINUX_SSB_H_
#ifdef __KERNEL__
#include <linux/device.h>
#include <linux/list.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#ifdef CONFIG_SSB_PCIHOST
# include <linux/pci.h>
#endif
#include <linux/pci.h>
#include <linux/mod_devicetable.h>
#include <linux/ssb/ssb_regs.h>
@@ -156,20 +154,6 @@ struct ssb_bus_ops {
/* Vendor-ID values */
#define SSB_VENDOR_BROADCOM 0x4243
struct ssb_device_id {
u16 vendor;
u16 coreid;
u8 revision;
};
#define SSB_DEVICE(_vendor, _coreid, _revision) \
{ .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
#define SSB_DEVTABLE_END \
{ 0, },
#define SSB_ANY_VENDOR 0xFFFF
#define SSB_ANY_ID 0xFFFF
#define SSB_ANY_REV 0xFF
/* Some kernel subsystems poke with dev->drvdata, so we must use the
* following ugly workaround to get from struct device to struct ssb_device */
struct __ssb_dev_wrapper {
@@ -198,7 +182,8 @@ struct ssb_device {
static inline
struct ssb_device * dev_to_ssb_dev(struct device *dev)
{
struct __ssb_dev_wrapper *wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
struct __ssb_dev_wrapper *wrap;
wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
return wrap->sdev;
}
@@ -296,6 +281,7 @@ struct ssb_bus {
struct pcmcia_device *host_pcmcia;
#ifdef CONFIG_SSB_PCIHOST
/* Mutex to protect the SPROM writing. */
struct mutex pci_sprom_mutex;
#endif
@@ -333,8 +319,13 @@ struct ssb_bus {
/* Contents of the SPROM. */
struct ssb_sprom sprom;
/* Internal. */
/* Internal-only stuff follows. Do not touch. */
struct list_head list;
#ifdef CONFIG_SSB_DEBUG
/* Is the bus already powered up? */
bool powered_up;
int power_warn_count;
#endif /* DEBUG */
};
/* The initialization-invariants. */
@@ -342,6 +333,9 @@ struct ssb_init_invariants {
struct ssb_boardinfo boardinfo;
struct ssb_sprom sprom;
};
/* Type of function to fetch the invariants. */
typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
struct ssb_init_invariants *iv);
/* Register a SSB system bus. get_invariants() is called after the
* basic system devices are initialized.
@@ -349,8 +343,7 @@ struct ssb_init_invariants {
* Put the invariants into the struct pointed to by iv. */
extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
unsigned long baseaddr,
int (*get_invariants)(struct ssb_bus *bus,
struct ssb_init_invariants *iv));
ssb_invariants_func_t get_invariants);
#ifdef CONFIG_SSB_PCIHOST
extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
struct pci_dev *host_pci);
@@ -365,8 +358,12 @@ extern void ssb_bus_unregister(struct ssb_bus *bus);
extern u32 ssb_clockspeed(struct ssb_bus *bus);
/* Is the device enabled in hardware? */
int ssb_device_is_enabled(struct ssb_device *dev);
/* Enable a device and pass device-specific SSB_TMSLOW flags.
* If no device-specific flags are available, use 0. */
void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
@@ -408,9 +405,15 @@ static inline void ssb_pcihost_unregister(struct pci_driver *driver)
#endif /* CONFIG_SSB_PCIHOST */
/* Bus-Power handling functions. */
/* If a driver is shutdown or suspended, call this to signal
* that the bus may be completely powered down. SSB will decide,
* if it's really time to power down the bus, based on if there
* are other devices that want to run. */
extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
extern int ssb_bus_powerup(struct ssb_bus *bus, int dynamic_pctl);
/* Before initializing and enabling a device, call this to power-up the bus.
* If you want to allow use of dynamic-power-control, pass the flag.
* Otherwise static always-on powercontrol will be used. */
extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
/* Various helper functions */
@@ -418,5 +421,4 @@ extern u32 ssb_admatch_base(u32 adm);
extern u32 ssb_admatch_size(u32 adm);
#endif /* __KERNEL__ */
#endif /* LINUX_SSB_H_ */

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@@ -12,7 +12,6 @@
*
* Licensed under the GPL version 2. See COPYING for details.
*/
#ifdef __KERNEL__
/** ChipCommon core registers. **/
@@ -364,6 +363,8 @@ extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m);
extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m);
extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
@@ -378,10 +379,18 @@ enum ssb_clkmode {
extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
enum ssb_clkmode mode);
extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
u32 ticks);
u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
#ifdef CONFIG_SSB_SERIAL
extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
struct ssb_serial_port *ports);
#endif /* CONFIG_SSB_SERIAL */
#endif /* __KERNEL__ */
#endif /* LINUX_SSB_CHIPCO_H_ */

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@@ -20,12 +20,6 @@
#ifndef LINUX_SSB_EXTIFCORE_H_
#define LINUX_SSB_EXTIFCORE_H_
#ifdef __KERNEL__
struct ssb_extif {
struct ssb_device *dev;
};
/* external interface address space */
#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x)
#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
@@ -159,5 +153,52 @@ struct ssb_extif {
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
#endif /* __KERNEL__ */
#ifdef CONFIG_SSB_DRIVER_EXTIF
struct ssb_extif {
struct ssb_device *dev;
};
static inline bool ssb_extif_available(struct ssb_extif *extif)
{
return (extif->dev != NULL);
}
extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
u32 *plltype, u32 *n, u32 *m);
extern void ssb_extif_timing_init(struct ssb_extif *extif,
unsigned long ns);
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
#ifdef CONFIG_SSB_SERIAL
extern int ssb_extif_serial_init(struct ssb_extif *extif,
struct ssb_serial_port *ports);
#endif /* CONFIG_SSB_SERIAL */
#else /* CONFIG_SSB_DRIVER_EXTIF */
/* extif disabled */
struct ssb_extif {
};
static inline bool ssb_extif_available(struct ssb_extif *extif)
{
return 0;
}
static inline
void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
u32 *plltype, u32 *n, u32 *m)
{
}
#endif /* CONFIG_SSB_DRIVER_EXTIF */
#endif /* LINUX_SSB_EXTIFCORE_H_ */

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@@ -1,8 +1,6 @@
#ifndef LINUX_SSB_MIPSCORE_H_
#define LINUX_SSB_MIPSCORE_H_
#ifdef __KERNEL__
#ifdef CONFIG_SSB_DRIVER_MIPS
struct ssb_device;
@@ -22,11 +20,13 @@ struct ssb_mipscore {
int nr_serial_ports;
struct ssb_serial_port serial_ports[4];
u8 flash_buswidth;
u32 flash_window;
u32 flash_window_size;
};
extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
extern unsigned int ssb_mips_irq(struct ssb_device *dev);
@@ -43,5 +43,4 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore)
#endif /* CONFIG_SSB_DRIVER_MIPS */
#endif /* __KERNEL__ */
#endif /* LINUX_SSB_MIPSCORE_H_ */

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@@ -1,6 +1,5 @@
#ifndef LINUX_SSB_PCICORE_H_
#define LINUX_SSB_PCICORE_H_
#ifdef __KERNEL__
#ifdef CONFIG_SSB_DRIVER_PCICORE
@@ -104,5 +103,4 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
}
#endif /* CONFIG_SSB_DRIVER_PCICORE */
#endif /* __KERNEL__ */
#endif /* LINUX_SSB_PCICORE_H_ */

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@@ -1,31 +1,30 @@
#ifndef LINUX_SSB_REGS_H_
#define LINUX_SSB_REGS_H_
#ifdef __KERNEL__
/* SiliconBackplane Address Map.
* All regions may not exist on all chips.
*/
#define SSB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
#define SSB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
#define SSB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
#define SSB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
#define SSB_ENUM_BASE 0x18000000 /* Enumeration space base */
#define SSB_ENUM_LIMIT 0x18010000 /* Enumeration space limit */
#define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
#define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
#define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
#define SSB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
#define SSB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
#define SSB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
#define SSB_FLASH1 0x1fc00000 /* Flash Region 1 */
#define SSB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
#define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
#define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
#define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */
#define SSB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SSB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
#define SSB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
#define SSB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
#define SSB_EUART (SB_EXTIF_BASE + 0x00800000)
#define SSB_LED (SB_EXTIF_BASE + 0x00900000)
#define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
#define SSB_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
#define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
#define SSB_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
/* Enumeration space constants */
@@ -268,7 +267,7 @@ enum {
SSB_SPROM1CCODE_NONE,
};
/* Address-Match values and masks (SSB_ADMATCH?) */
/* Address-Match values and masks (SSB_ADMATCHxxx) */
#define SSB_ADM_TYPE 0x00000003 /* Address type */
#define SSB_ADM_TYPE0 0
#define SSB_ADM_TYPE1 1
@@ -290,5 +289,4 @@ enum {
#define SSB_ADM_BASE2_SHIFT 16
#endif /* __KERNEL__ */
#endif /* LINUX_SSB_REGS_H_ */