e0e74d8a2c
swig has been installed on the buildbots a while a ago and Petr Štetiar got a fix for the pylibfdt error. Use that and re-enable the builds for mt7620 and mt7621. Refresh patches while at it. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
57 lines
1.5 KiB
Diff
57 lines
1.5 KiB
Diff
From 03035a6566300808c8845799b2f9ceca471aa61a Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 20 May 2022 11:22:41 +0800
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Subject: [PATCH 09/25] reset: mtmips: add reset controller support for
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MediaTek MT7621 SoC
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This patch adds reset controller bits definition header file for MediaTek
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MT7621 SoC
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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include/dt-bindings/reset/mt7621-reset.h | 38 ++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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create mode 100644 include/dt-bindings/reset/mt7621-reset.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/mt7621-reset.h
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@@ -0,0 +1,38 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
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+ *
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+ * Author: Weijie Gao <weijie.gao@mediatek.com>
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+ */
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+
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+#ifndef _DT_BINDINGS_MT7621_RESET_H_
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+#define _DT_BINDINGS_MT7621_RESET_H_
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+
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+#define RST_PPE 31
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+#define RST_SDXC 30
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+#define RST_CRYPTO 29
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+#define RST_AUX_STCK 28
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+#define RST_PCIE2 26
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+#define RST_PCIE1 25
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+#define RST_PCIE0 24
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+#define RST_GMAC 23
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+#define RST_UART3 21
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+#define RST_UART2 20
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+#define RST_UART1 19
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+#define RST_SPI 18
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+#define RST_I2S 17
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+#define RST_I2C 16
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+#define RST_NFI 15
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+#define RST_GDMA 14
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+#define RST_PIO 13
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+#define RST_PCM 11
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+#define RST_MC 10
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+#define RST_INTC 9
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+#define RST_TIMER 8
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+#define RST_SPDIFTX 7
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+#define RST_FE 6
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+#define RST_HSDMA 5
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+#define RST_MCM 2
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+#define RST_SYS 0
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+
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+#endif /* _DT_BINDINGS_MT7621_RESET_H_ */
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