0ea329fec4
Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
101 lines
3.1 KiB
Diff
101 lines
3.1 KiB
Diff
From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:04:29 +0800
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Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986
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This patch adds support for MediaTek MT7981 and MT7986. Both chips uses
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PDMA v2.
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Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/net/mtk_eth.c | 27 +++++++++++++++++++++++++++
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drivers/net/mtk_eth.h | 5 +++++
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2 files changed, 32 insertions(+)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -115,6 +115,7 @@ struct mtk_eth_priv {
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int force_mode;
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int speed;
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int duplex;
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+ bool pn_swap;
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struct phy_device *phydev;
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int phy_interface;
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@@ -1057,6 +1058,12 @@ static void mtk_sgmii_init(struct mtk_et
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/* SGMII force mode setting */
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writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
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+ /* SGMII PN SWAP setting */
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+ if (priv->pn_swap) {
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+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
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+ SGMII_PN_SWAP_TX_RX);
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+ }
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+
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/* Release PHYA power down state */
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clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, 0);
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@@ -1470,6 +1477,8 @@ static int mtk_eth_of_to_plat(struct ude
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dev_err(dev, "Unable to find sgmii\n");
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return -ENODEV;
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}
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+
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+ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
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}
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/* check for switch first, otherwise phy will be used */
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@@ -1520,6 +1529,22 @@ static int mtk_eth_of_to_plat(struct ude
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return 0;
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}
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+static const struct mtk_soc_data mt7986_data = {
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+ .caps = MT7986_CAPS,
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+ .ana_rgc3 = 0x128,
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+ .pdma_base = PDMA_V2_BASE,
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+ .txd_size = sizeof(struct mtk_tx_dma_v2),
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+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
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+};
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+
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+static const struct mtk_soc_data mt7981_data = {
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+ .caps = MT7986_CAPS,
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+ .ana_rgc3 = 0x128,
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+ .pdma_base = PDMA_V2_BASE,
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+ .txd_size = sizeof(struct mtk_tx_dma_v2),
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+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
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+};
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+
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static const struct mtk_soc_data mt7629_data = {
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.ana_rgc3 = 0x128,
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.pdma_base = PDMA_V1_BASE,
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@@ -1549,6 +1574,8 @@ static const struct mtk_soc_data mt7621_
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};
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static const struct udevice_id mtk_eth_ids[] = {
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+ { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
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+ { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
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{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
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{ .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
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{ .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
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--- a/drivers/net/mtk_eth.h
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+++ b/drivers/net/mtk_eth.h
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@@ -36,6 +36,8 @@ enum mkt_eth_capabilities {
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#define MT7623_CAPS (MTK_GMAC1_TRGMII)
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+#define MT7986_CAPS (MTK_NETSYS_V2)
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+
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/* Frame Engine Register Bases */
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#define PDMA_V1_BASE 0x0800
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#define PDMA_V2_BASE 0x6000
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@@ -72,6 +74,9 @@ enum mkt_eth_capabilities {
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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+#define SGMSYS_QPHY_WRAP_CTRL 0xec
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+#define SGMII_PN_SWAP_TX_RX 0x03
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+
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_GEN2_SPEED_V2 0x128
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#define SGMSYS_SPEED_2500 BIT(2)
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