8cc2caed58
Refresh patch for 5.15 Rework tweak patch to sync with upstream ipq8064 dtsi and fix regression introduced. Rename nand_controller to nand in every dts. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
45 lines
1.2 KiB
Diff
45 lines
1.2 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -689,6 +689,41 @@
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reg = <0x12100000 0x10000>;
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};
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+ gsbi1: gsbi@12440000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <1>;
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+ reg = <0x12440000 0x100>;
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+ clocks = <&gcc GSBI1_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ syscon-tcsr = <&tcsr>;
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+
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+ gsbi1_serial: serial@12450000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x12450000 0x100>,
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+ <0x12400000 0x03>;
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ gsbi1_i2c: i2c@12460000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x12460000 0x1000>;
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+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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