 3e1c92f9e1
			
		
	
	3e1c92f9e1
	
	
	
		
			
			Manually rebased: ath79/patches-5.4/0033-spi-ath79-drop-pdata-support.patch Removed uneeded patch: ath79/patches-5.4/0050-spi-ath79-remove-spi-master-setup-and-cleanup-assign.patch All other patches automatically rebased. Build system: x86_64 Build-tested: ipq806x/R7800 Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us>
		
			
				
	
	
		
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			69 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001
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| From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
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| Date: Mon, 10 Feb 2020 16:11:27 -0300
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| Subject: [PATCH] spi: ath79: Implement the spi_mem interface
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| 
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| Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
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| ---
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|  drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++
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|  1 file changed, 35 insertions(+)
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| 
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| --- a/drivers/spi/spi-ath79.c
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| +++ b/drivers/spi/spi-ath79.c
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| @@ -15,6 +15,7 @@
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|  #include <linux/platform_device.h>
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|  #include <linux/io.h>
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|  #include <linux/spi/spi.h>
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| +#include <linux/spi/spi-mem.h>
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|  #include <linux/spi/spi_bitbang.h>
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|  #include <linux/bitops.h>
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|  #include <linux/clk.h>
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| @@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s
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|  	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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|  }
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|  
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| +static int ath79_exec_mem_op(struct spi_mem *mem,
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| +                              const struct spi_mem_op *op)
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| +{
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| +	struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
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| +
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| +	/* Ensures that reading is performed on device connected
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| +	   to hardware cs0 */
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| +	if (mem->spi->chip_select || mem->spi->cs_gpiod)
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| +		return -ENOTSUPP;
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| +
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| +	/* Only use for fast-read op. */
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| +	if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
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| +	    op->addr.nbytes != 3 || op->dummy.nbytes != 1)
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| +		return -ENOTSUPP;
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| +
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| +	/* disable GPIO mode */
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| +	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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| +
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| +	memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
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| +
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| +	/* enable GPIO mode */
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| +	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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| +
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| +	/* restore IOC register */
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| +	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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| +
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| +	return 0;
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| +}
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| +
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| +static const struct spi_controller_mem_ops ath79_mem_ops = {
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| +	.exec_op = ath79_exec_mem_op,
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| +};
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| +
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|  static int ath79_spi_probe(struct platform_device *pdev)
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|  {
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|  	struct spi_master *master;
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| @@ -164,6 +198,7 @@ static int ath79_spi_probe(struct platfo
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|  		ret = PTR_ERR(sp->base);
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|  		goto err_put_master;
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|  	}
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| +	master->mem_ops = &ath79_mem_ops;
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|  
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|  	sp->clk = devm_clk_get(&pdev->dev, "ahb");
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|  	if (IS_ERR(sp->clk)) {
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