0224e32cd0
This backports upstream commit 62e13097c46c ("net: phy: broadcom: rehook
BCM54612E specific init")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
160 lines
5.3 KiB
Diff
160 lines
5.3 KiB
Diff
--- a/drivers/net/phy/broadcom.c
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+++ b/drivers/net/phy/broadcom.c
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@@ -30,6 +30,50 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
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MODULE_AUTHOR("Maciej W. Rozycki");
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MODULE_LICENSE("GPL");
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+static int bcm54210e_config_init(struct phy_device *phydev)
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+{
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+ int val;
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+
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+ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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+ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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+ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
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+
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+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
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+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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+ bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
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+
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+ return 0;
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+}
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+
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+static int bcm54612e_config_init(struct phy_device *phydev)
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+{
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+ /* Clear TX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
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+ /* Disable TXD to GTXCLK clock delay (default set) */
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+ /* Bit 9 is the only field in shadow register 00011 */
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+ bcm_phy_write_shadow(phydev, 0x03, 0);
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+ }
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+
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+ /* Clear RX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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+ u16 reg;
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+
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+ reg = bcm54xx_auxctl_read(phydev,
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+ MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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+ /* Disable RXD to RXC delay (default set) */
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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+ /* Clear shadow selector field */
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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+ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
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+ }
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+
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+ return 0;
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+}
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+
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static int bcm54810_config(struct phy_device *phydev)
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{
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int rc, val;
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@@ -230,7 +274,15 @@ static int bcm54xx_config_init(struct ph
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(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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bcm54xx_adjust_rxrefclk(phydev);
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- if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
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+ err = bcm54210e_config_init(phydev);
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+ if (err)
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+ return err;
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+ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
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+ err = bcm54612e_config_init(phydev);
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+ if (err)
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+ return err;
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+ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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err = bcm54810_config(phydev);
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if (err)
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return err;
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@@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
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return ret;
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}
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-static int bcm54612e_config_aneg(struct phy_device *phydev)
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-{
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- int ret;
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-
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- /* First, auto-negotiate. */
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- ret = genphy_config_aneg(phydev);
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-
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- /* Clear TX internal delay unless requested. */
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- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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- (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
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- /* Disable TXD to GTXCLK clock delay (default set) */
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- /* Bit 9 is the only field in shadow register 00011 */
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- bcm_phy_write_shadow(phydev, 0x03, 0);
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- }
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-
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- /* Clear RX internal delay unless requested. */
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- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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- (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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- u16 reg;
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-
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- /* Errata: reads require filling in the write selector field */
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- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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- MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
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- reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
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- /* Disable RXD to RXC delay (default set) */
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- reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
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- /* Clear shadow selector field */
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- reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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- MII_BCM54XX_AUXCTL_MISC_WREN | reg);
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- }
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-
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- return ret;
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-}
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-
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static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
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{
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int val;
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@@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver
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.config_intr = bcm_phy_config_intr,
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.driver = { .owner = THIS_MODULE },
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}, {
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+ .phy_id = PHY_ID_BCM54210E,
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+ .phy_id_mask = 0xfffffff0,
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+ .name = "Broadcom BCM54210E",
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+ .features = PHY_GBIT_FEATURES |
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+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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+ .config_init = bcm54xx_config_init,
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+ .config_aneg = genphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = bcm_phy_ack_intr,
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+ .config_intr = bcm_phy_config_intr,
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+ .driver = { .owner = THIS_MODULE },
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+}, {
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.phy_id = PHY_ID_BCM5461,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5461",
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@@ -568,7 +598,7 @@ static struct phy_driver broadcom_driver
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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- .config_aneg = bcm54612e_config_aneg,
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+ .config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm_phy_ack_intr,
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.config_intr = bcm_phy_config_intr,
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@@ -710,6 +740,7 @@ module_phy_driver(broadcom_drivers);
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static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
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{ PHY_ID_BCM5411, 0xfffffff0 },
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{ PHY_ID_BCM5421, 0xfffffff0 },
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+ { PHY_ID_BCM54210E, 0xfffffff0 },
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{ PHY_ID_BCM5461, 0xfffffff0 },
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{ PHY_ID_BCM54612E, 0xfffffff0 },
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{ PHY_ID_BCM54616S, 0xfffffff0 },
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--- a/include/linux/brcmphy.h
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+++ b/include/linux/brcmphy.h
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@@ -17,6 +17,7 @@
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#define PHY_ID_BCM5482 0x0143bcb0
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#define PHY_ID_BCM5411 0x00206070
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#define PHY_ID_BCM5421 0x002060e0
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+#define PHY_ID_BCM54210E 0x600d84a0
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#define PHY_ID_BCM5464 0x002060b0
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#define PHY_ID_BCM5461 0x002060c0
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#define PHY_ID_BCM54612E 0x03625e60
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