Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
		
			
				
	
	
		
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			111 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
From 8464c7b6e7c491ae06b18103881611c98678cf1f Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.Wang@nxp.com>
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Date: Thu, 13 Apr 2017 14:54:01 -0400
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Subject: [PATCH] soc: fsl: dpio: enable qbman CENA portal memory access
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Once we enable the cacheable portal memory, we need to do
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cache flush for enqueue, vdq, buffer release, and management
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commands, as well as invalidate and prefetch for the valid bit
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of management command response and next index of dqrr.
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Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
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---
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 drivers/soc/fsl/dpio/qbman-portal.c | 23 +++++++++++++++++------
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 1 file changed, 17 insertions(+), 6 deletions(-)
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--- a/drivers/soc/fsl/dpio/qbman-portal.c
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+++ b/drivers/soc/fsl/dpio/qbman-portal.c
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@@ -90,6 +90,14 @@ enum qbman_sdqcr_fc {
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 	qbman_sdqcr_fc_up_to_3 = 1
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 };
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+#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
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+#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
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+static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
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+{
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+	dcivac(p->addr_cena + offset);
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+	prefetch(p->addr_cena + offset);
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+}
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+
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 /* Portal Access */
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 static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
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@@ -190,7 +198,7 @@ struct qbman_swp *qbman_swp_init(const s
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 		memset(p->addr_cena, 0, 64 * 1024);
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 	reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
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-				1, /* Writes Non-cacheable */
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+				0, /* Writes cacheable */
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 				0, /* EQCR_CI stashing threshold */
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 				3, /* RPM: Valid bit mode, RCR in array mode */
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 				2, /* DCM: Discrete consumption ack mode */
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@@ -329,6 +337,7 @@ void qbman_swp_mc_submit(struct qbman_sw
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 	if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) {
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 		dma_wmb();
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 		*v = cmd_verb | p->mc.valid_bit;
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+		dccvac(cmd);
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 	} else {
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 		*v = cmd_verb | p->mc.valid_bit;
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 		dma_wmb();
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@@ -345,6 +354,7 @@ void *qbman_swp_mc_result(struct qbman_s
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 	u32 *ret, verb;
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 	if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) {
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+		qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
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 		ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
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 		/* Remove the valid-bit - command completed if the rest
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 		 * is non-zero.
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@@ -481,6 +491,7 @@ int qbman_swp_enqueue(struct qbman_swp *
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 		/* Set the verb byte, have to substitute in the valid-bit */
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 		dma_wmb();
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 		p->verb = d->verb | EQAR_VB(eqar);
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+		dccvac(p);
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 	} else {
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 		p->verb = d->verb | EQAR_VB(eqar);
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 		dma_wmb();
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@@ -677,6 +688,7 @@ int qbman_swp_pull(struct qbman_swp *s,
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 		/* Set the verb byte, have to substitute in the valid-bit */
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 		p->verb = d->verb | s->vdq.valid_bit;
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 		s->vdq.valid_bit ^= QB_VALID_BIT;
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+		dccvac(p);
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 	} else {
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 		p->verb = d->verb | s->vdq.valid_bit;
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 		s->vdq.valid_bit ^= QB_VALID_BIT;
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@@ -736,8 +748,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
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 				 s->dqrr.next_idx, pi);
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 			s->dqrr.reset_bug = 0;
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 		}
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-		prefetch(qbman_get_cmd(s,
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-				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
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+		qbman_inval_prefetch(s,	QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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 	}
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 	if ((s->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000)
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@@ -755,8 +766,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
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 	 * knew from reading PI.
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 	 */
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 	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
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-		prefetch(qbman_get_cmd(s,
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-				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
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+		qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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 		return NULL;
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 	}
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 	/*
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@@ -779,7 +789,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
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 	    (flags & DPAA2_DQ_STAT_EXPIRED))
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 		atomic_inc(&s->vdq.available);
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-	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
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+	qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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 	return p;
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 }
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@@ -911,6 +921,7 @@ int qbman_swp_release(struct qbman_swp *
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 		 */
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 		dma_wmb();
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 		p->verb = d->verb | RAR_VB(rar) | num_buffers;
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+		dccvac(p);
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 	} else {
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 		p->verb = d->verb | RAR_VB(rar) | num_buffers;
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 		dma_wmb();
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