 92eb27f56d
			
		
	
	92eb27f56d
	
	
	
		
			
			Remove the need for the header file to be exported - we don't need most of it anyway; all we care about are the offset of the rootfs length and header crc fields. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 44557
		
			
				
	
	
		
			59 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
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			59 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From 85f7cdacbb81db8c4cc8e474837eab1f0e4ff77b Mon Sep 17 00:00:00 2001
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| From: Andrew Bresticker <abrestic@chromium.org>
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| Date: Thu, 18 Sep 2014 14:47:09 -0700
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| Subject: [PATCH 3/3] MIPS: Provide a generic plat_irq_dispatch
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| 
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| For platforms which boot with device-tree or have correctly chained
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| all external interrupt controllers, a generic plat_irq_dispatch() can
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| be used.  Implement a plat_irq_dispatch() which simply handles all the
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| pending interrupts as reported by C0_Cause.
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| 
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| Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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| Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
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| Tested-by: Qais Yousef <qais.yousef@imgtec.com>
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| Cc: Thomas Gleixner <tglx@linutronix.de>
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| Cc: Jason Cooper <jason@lakedaemon.net>
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| Cc: Andrew Bresticker <abrestic@chromium.org>
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| Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
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| Cc: Markos Chandras <markos.chandras@imgtec.com>
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| Cc: Paul Burton <paul.burton@imgtec.com>
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| Cc: Qais Yousef <qais.yousef@imgtec.com>
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| Cc: Jonas Gorski <jogo@openwrt.org>
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| Cc: John Crispin <blogic@openwrt.org>
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| Cc: David Daney <ddaney.cavm@gmail.com>
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| Cc: linux-mips@linux-mips.org
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| Cc: linux-kernel@vger.kernel.org
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| Patchwork: https://patchwork.linux-mips.org/patch/7801/
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| Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| ---
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|  arch/mips/kernel/irq_cpu.c |   18 ++++++++++++++++++
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|  1 file changed, 18 insertions(+)
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| 
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| --- a/arch/mips/kernel/irq_cpu.c
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| +++ b/arch/mips/kernel/irq_cpu.c
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| @@ -98,6 +98,24 @@ static struct irq_chip mips_mt_cpu_irq_c
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|  	.irq_enable	= unmask_mips_irq,
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|  };
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|  
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| +asmlinkage void __weak plat_irq_dispatch(void)
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| +{
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| +	unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
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| +	int irq;
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| +
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| +	if (!pending) {
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| +		spurious_interrupt();
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| +		return;
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| +	}
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| +
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| +	pending >>= CAUSEB_IP;
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| +	while (pending) {
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| +		irq = fls(pending) - 1;
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| +		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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| +		pending &= ~BIT(irq);
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| +	}
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| +}
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| +
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|  static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
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|  			     irq_hw_number_t hw)
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|  {
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