387fd3ca26
Add 3.18 support based on 3.18-rc6. Only netboot tested. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 43461
71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 8 Dec 2013 03:13:06 +0100
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Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows
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Different SoCs use different memory windows (and sizes), so don't
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hardcode it.
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++++----
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arch/mips/pci/pci-bcm63xx.c | 15 ++++++++++-----
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2 files changed, 14 insertions(+), 9 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -40,10 +40,10 @@
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#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
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BCM_CB_MEM_SIZE - 1)
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-#define BCM_PCIE_MEM_BASE_PA 0x10f00000
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-#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024)
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-#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
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- BCM_PCIE_MEM_SIZE - 1)
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+#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000
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+#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024)
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+#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \
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+ BCM_PCIE_MEM_SIZE_6328 - 1)
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/*
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* Internal registers are accessed through KSEG3
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control
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static struct resource bcm_pcie_mem_resource = {
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.name = "bcm63xx PCIe memory space",
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- .start = BCM_PCIE_MEM_BASE_PA,
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- .end = BCM_PCIE_MEM_END_PA,
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+ .start = 0,
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+ .end = 0,
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.flags = IORESOURCE_MEM,
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};
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@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(
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bcm_pcie_writel(val, PCIE_CONFIG2_REG);
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/* set bar0 to little endian */
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- val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
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- val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
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+ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
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+ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
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val |= BASEMASK_REMAP_EN;
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
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- val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
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+ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
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register_pci_controller(&bcm63xx_pcie_controller);
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@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)
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if (!bcm63xx_pci_enabled)
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return -ENODEV;
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
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+ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
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+ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
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+ }
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+
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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case BCM6362_CPU_ID:
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