30d2fcffeb
The prerequisite DSA changes for the nice RTL8366RB improvements are already backported so bring back these changes as well. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
108 lines
3.4 KiB
Diff
108 lines
3.4 KiB
Diff
From 90c855471a89d3e05ecf5b6464bd04abf2c83b70 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Tue, 5 Oct 2021 21:47:04 +0200
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Subject: [PATCH 10/11] net: dsa: rtl8366rb: Support setting STP state
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This adds support for setting the STP state to the RTL8366RB
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DSA switch. This rids the following message from the kernel on
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e.g. OpenWrt:
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DSA: failed to set STP state 3 (-95)
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Since the RTL8366RB has one STP state register per FID with
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two bit per port in each, we simply loop over all the FIDs
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and set the state on all of them.
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Cc: Vladimir Oltean <olteanv@gmail.com>
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Cc: Alvin Šipraga <alsi@bang-olufsen.dk>
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Cc: Mauri Sandberg <sandberg@mailfence.com>
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Cc: DENG Qingfang <dqfext@gmail.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/rtl8366rb.c | 48 +++++++++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/net/dsa/rtl8366rb.c
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+++ b/drivers/net/dsa/rtl8366rb.c
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@@ -110,6 +110,18 @@
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#define RTL8366RB_POWER_SAVING_REG 0x0021
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+/* Spanning tree status (STP) control, two bits per port per FID */
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+#define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
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+#define RTL8366RB_STP_STATE_DISABLED 0x0
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+#define RTL8366RB_STP_STATE_BLOCKING 0x1
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+#define RTL8366RB_STP_STATE_LEARNING 0x2
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+#define RTL8366RB_STP_STATE_FORWARDING 0x3
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+#define RTL8366RB_STP_MASK GENMASK(1, 0)
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+#define RTL8366RB_STP_STATE(port, state) \
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+ ((state) << ((port) * 2))
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+#define RTL8366RB_STP_STATE_MASK(port) \
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+ RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
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+
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/* CPU port control reg */
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#define RTL8368RB_CPU_CTRL_REG 0x0061
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#define RTL8368RB_CPU_PORTS_MSK 0x00FF
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@@ -234,6 +246,7 @@
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#define RTL8366RB_NUM_LEDGROUPS 4
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#define RTL8366RB_NUM_VIDS 4096
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#define RTL8366RB_PRIORITYMAX 7
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+#define RTL8366RB_NUM_FIDS 8
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#define RTL8366RB_FIDMAX 7
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#define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
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@@ -1309,6 +1322,40 @@ rtl8366rb_port_bridge_flags(struct dsa_s
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}
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static void
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+rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
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+{
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+ struct realtek_smi *smi = ds->priv;
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+ u32 val;
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+ int i;
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+
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+ switch (state) {
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+ case BR_STATE_DISABLED:
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+ val = RTL8366RB_STP_STATE_DISABLED;
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+ break;
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+ case BR_STATE_BLOCKING:
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+ case BR_STATE_LISTENING:
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+ val = RTL8366RB_STP_STATE_BLOCKING;
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+ break;
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+ case BR_STATE_LEARNING:
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+ val = RTL8366RB_STP_STATE_LEARNING;
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+ break;
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+ case BR_STATE_FORWARDING:
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+ val = RTL8366RB_STP_STATE_FORWARDING;
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+ break;
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+ default:
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+ dev_err(smi->dev, "unknown bridge state requested\n");
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+ return;
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+ };
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+
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+ /* Set the same status for the port on all the FIDs */
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+ for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
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+ regmap_update_bits(smi->map, RTL8366RB_STP_STATE_BASE + i,
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+ RTL8366RB_STP_STATE_MASK(port),
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+ RTL8366RB_STP_STATE(port, val));
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+ }
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+}
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+
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+static void
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rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
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{
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struct realtek_smi *smi = ds->priv;
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@@ -1733,6 +1780,7 @@ static const struct dsa_switch_ops rtl83
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.port_disable = rtl8366rb_port_disable,
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.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
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.port_bridge_flags = rtl8366rb_port_bridge_flags,
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+ .port_stp_state_set = rtl8366rb_port_stp_state_set,
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.port_fast_age = rtl8366rb_port_fast_age,
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.port_change_mtu = rtl8366rb_change_mtu,
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.port_max_mtu = rtl8366rb_max_mtu,
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