f4d949b404
Backport qca8k fixup for mgmt and mdio read/write for kernel 5.15 fixup port dropping and configuration issue. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Robert Marko <robimarko@gmail.com>
151 lines
3.4 KiB
Diff
151 lines
3.4 KiB
Diff
From cfbd6de588ef659c198083205dc954a6d3ed2aec Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 29 Dec 2022 17:33:35 +0100
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Subject: [PATCH 4/5] net: dsa: qca8k: introduce single mii read/write lo/hi
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It may be useful to read/write just the lo or hi half of a reg.
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This is especially useful for phy poll with the use of mdio master.
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The mdio master reg is composed by the first 16 bit related to setup and
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the other half with the returned data or data to write.
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Refactor the mii function to permit single mii read/write of lo or hi
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half of the reg.
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Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 106 ++++++++++++++++++++++++-------
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1 file changed, 84 insertions(+), 22 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -37,42 +37,104 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
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}
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static int
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-qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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+qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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{
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int ret;
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+ u16 lo;
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- ret = bus->read(bus, phy_id, regnum);
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- if (ret >= 0) {
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- *val = ret;
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- ret = bus->read(bus, phy_id, regnum + 1);
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- *val |= ret << 16;
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- }
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+ lo = val & 0xffff;
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+ ret = bus->write(bus, phy_id, regnum, lo);
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+ if (ret < 0)
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to write qca8k 32bit lo register\n");
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+
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+ return ret;
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+}
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- if (ret < 0) {
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+static int
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+qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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+{
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+ int ret;
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+ u16 hi;
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+
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+ hi = (u16)(val >> 16);
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+ ret = bus->write(bus, phy_id, regnum, hi);
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+ if (ret < 0)
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dev_err_ratelimited(&bus->dev,
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- "failed to read qca8k 32bit register\n");
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- *val = 0;
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- return ret;
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- }
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+ "failed to write qca8k 32bit hi register\n");
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+ return ret;
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+}
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+
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+static int
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+qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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+{
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+ int ret;
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+
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+ ret = bus->read(bus, phy_id, regnum);
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+ if (ret < 0)
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+ goto err;
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+
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+ *val = ret & 0xffff;
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return 0;
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+
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+err:
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to read qca8k 32bit lo register\n");
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+ *val = 0;
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+
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+ return ret;
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}
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-static void
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-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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+static int
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+qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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{
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- u16 lo, hi;
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int ret;
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- lo = val & 0xffff;
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- hi = (u16)(val >> 16);
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+ ret = bus->read(bus, phy_id, regnum);
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+ if (ret < 0)
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+ goto err;
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- ret = bus->write(bus, phy_id, regnum, lo);
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- if (ret >= 0)
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- ret = bus->write(bus, phy_id, regnum + 1, hi);
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+ *val = ret << 16;
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+ return 0;
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+
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+err:
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to read qca8k 32bit hi register\n");
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+ *val = 0;
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+
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+ return ret;
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+}
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+
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+static int
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+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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+{
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+ u32 hi, lo;
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+ int ret;
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+
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+ *val = 0;
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+
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+ ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
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if (ret < 0)
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- dev_err_ratelimited(&bus->dev,
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- "failed to write qca8k 32bit register\n");
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+ goto err;
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+
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+ ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
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+ if (ret < 0)
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+ goto err;
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+
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+ *val = lo | hi;
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+
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+err:
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+ return ret;
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+}
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+
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+static void
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+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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+{
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+ if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
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+ return;
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+
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+ qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
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}
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static int
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