e4bad5f0ac
The following patches were integrated upstream: * target/linux/ipq40xx/patches-4.14/050-0006-mtd-nand-qcom-Add-a-NULL-check-for-devm_kasprintf.patch * target/linux/mediatek/patches-4.14/0177-phy-phy-mtk-tphy-use-auto-instead-of-force-to-bypass.patch This fixes tries to work around the following security problems: * CVE-2018-3620 L1 Terminal Fault OS, SMM related aspects * CVE-2018-3646 L1 Terminal Fault Virtualization related aspects Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
87 lines
2.4 KiB
Diff
87 lines
2.4 KiB
Diff
From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001
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From: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Date: Thu, 21 Sep 2017 18:31:49 +0800
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Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback
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This is used to force PHY with USB OTG function to enter a specific
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mode, and override OTG IDPIN(or IDDIG) signal.
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Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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---
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drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/drivers/phy/mediatek/phy-mtk-tphy.c
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+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
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@@ -96,9 +96,11 @@
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#define U3P_U2PHYDTM1 0x06C
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#define P2C_RG_UART_EN BIT(16)
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+#define P2C_FORCE_IDDIG BIT(9)
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#define P2C_RG_VBUSVALID BIT(5)
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#define P2C_RG_SESSEND BIT(4)
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#define P2C_RG_AVALID BIT(2)
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+#define P2C_RG_IDDIG BIT(1)
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#define U3P_U3_CHIP_GPIO_CTLD 0x0c
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#define P3C_REG_IP_SW_RST BIT(31)
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@@ -580,6 +582,31 @@ static void u2_phy_instance_exit(struct
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}
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}
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+static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
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+ struct mtk_phy_instance *instance,
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+ enum phy_mode mode)
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+{
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+ struct u2phy_banks *u2_banks = &instance->u2_banks;
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+ u32 tmp;
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+
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+ tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
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+ switch (mode) {
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+ case PHY_MODE_USB_DEVICE:
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+ tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
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+ break;
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+ case PHY_MODE_USB_HOST:
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+ tmp |= P2C_FORCE_IDDIG;
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+ tmp &= ~P2C_RG_IDDIG;
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+ break;
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+ case PHY_MODE_USB_OTG:
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+ tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
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+ break;
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+ default:
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+ return;
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+ }
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+ writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
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+}
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+
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static void pcie_phy_instance_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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@@ -876,6 +903,17 @@ static int mtk_phy_exit(struct phy *phy)
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return 0;
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}
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+static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
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+{
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+ struct mtk_phy_instance *instance = phy_get_drvdata(phy);
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+ struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
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+
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+ if (instance->type == PHY_TYPE_USB2)
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+ u2_phy_instance_set_mode(tphy, instance, mode);
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+
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+ return 0;
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+}
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+
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static struct phy *mtk_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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@@ -926,6 +964,7 @@ static const struct phy_ops mtk_tphy_ops
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.exit = mtk_phy_exit,
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.power_on = mtk_phy_power_on,
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.power_off = mtk_phy_power_off,
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+ .set_mode = mtk_phy_set_mode,
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.owner = THIS_MODULE,
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};
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