64b53247c4
Refresh patches. Remove upstreamed patch: generic/pending/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Update patches that no longer applies: generic/hack/901-debloat_sock_diag.patch Compile-tested on: x86/64. Runtime-tested on: x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
85 lines
2.3 KiB
Diff
85 lines
2.3 KiB
Diff
From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Fri, 29 Dec 2017 10:45:07 +0800
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Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes
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add ethernet device nodes which enable GMAC1 with SGMII interface
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++
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2 files changed, 53 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -249,6 +249,28 @@
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status = "okay";
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};
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+ð {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <ð_pins>;
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+ status = "okay";
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+
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+ gmac1: mac@1 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <1>;
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+ phy-handle = <&phy5>;
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+ };
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+
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+ mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy5: ethernet-phy@5 {
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+ reg = <5>;
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+ phy-mode = "sgmii";
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+ };
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+ };
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+};
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+
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -550,6 +550,37 @@
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#reset-cells = <1>;
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};
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+ eth: ethernet@1b100000 {
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+ compatible = "mediatek,mt7622-eth",
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+ "mediatek,mt2701-eth",
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+ "syscon";
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+ reg = <0 0x1b100000 0 0x20000>;
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+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
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+ <ðsys CLK_ETH_ESW_EN>,
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+ <ðsys CLK_ETH_GP0_EN>,
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+ <ðsys CLK_ETH_GP1_EN>,
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+ <ðsys CLK_ETH_GP2_EN>,
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+ <&sgmiisys CLK_SGMII_TX250M_EN>,
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+ <&sgmiisys CLK_SGMII_RX250M_EN>,
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+ <&sgmiisys CLK_SGMII_CDR_REF>,
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+ <&sgmiisys CLK_SGMII_CDR_FB>,
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+ <&topckgen CLK_TOP_SGMIIPLL>,
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+ <&apmixedsys CLK_APMIXED_ETH2PLL>;
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+ clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
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+ "sgmii_tx250m", "sgmii_rx250m",
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+ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
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+ "eth2pll";
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
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+ mediatek,ethsys = <ðsys>;
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+ mediatek,sgmiisys = <&sgmiisys>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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sgmiisys: sgmiisys@1b128000 {
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compatible = "mediatek,mt7622-sgmiisys",
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"syscon";
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