e842e16f45
- Refresh all patches - Removed upstreamed - Adapted 1 Compile tested on: bcm53xx, cns3xxx, imx6, lantiq Run tested on: cns3xxx & imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> [update from 4.9.28 to 4.9.29] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
195 lines
5.2 KiB
Diff
195 lines
5.2 KiB
Diff
From 112ef1882e12094c823937f9d72f2f598db02df7 Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Thu, 20 Oct 2016 16:56:38 +0800
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Subject: [PATCH 2/2] soc: mediatek: Add MT2701 scpsys driver
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Add scpsys driver for MT2701.
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mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
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be enabled on both arm64 and arm platforms.
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Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
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Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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Reviewed-by: Kevin Hilman <khilman@baylibre.com>
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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drivers/soc/mediatek/Kconfig | 2 +-
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drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
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2 files changed, 117 insertions(+), 2 deletions(-)
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--- a/drivers/soc/mediatek/Kconfig
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+++ b/drivers/soc/mediatek/Kconfig
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@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
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config MTK_SCPSYS
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bool "MediaTek SCPSYS Support"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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- default ARM64 && ARCH_MEDIATEK
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+ default ARCH_MEDIATEK
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select REGMAP
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select MTK_INFRACFG
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select PM_GENERIC_DOMAINS if PM
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--- a/drivers/soc/mediatek/mtk-scpsys.c
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+++ b/drivers/soc/mediatek/mtk-scpsys.c
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@@ -20,6 +20,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/soc/mediatek/infracfg.h>
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+#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/power/mt8173-power.h>
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#define SPM_VDE_PWR_CON 0x0210
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@@ -27,8 +28,13 @@
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#define SPM_VEN_PWR_CON 0x0230
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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+#define SPM_CONN_PWR_CON 0x0280
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#define SPM_VEN2_PWR_CON 0x0298
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-#define SPM_AUDIO_PWR_CON 0x029c
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+#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
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+#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
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+#define SPM_ETH_PWR_CON 0x02a0
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+#define SPM_HIF_PWR_CON 0x02a4
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+#define SPM_IFR_MSC_PWR_CON 0x02a8
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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@@ -42,10 +48,15 @@
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#define PWR_ON_2ND_BIT BIT(3)
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#define PWR_CLK_DIS_BIT BIT(4)
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+#define PWR_STATUS_CONN BIT(1)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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#define PWR_STATUS_VDEC BIT(7)
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+#define PWR_STATUS_BDP BIT(14)
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+#define PWR_STATUS_ETH BIT(15)
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+#define PWR_STATUS_HIF BIT(16)
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+#define PWR_STATUS_IFR_MSC BIT(17)
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#define PWR_STATUS_VENC_LT BIT(20)
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#define PWR_STATUS_VENC BIT(21)
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#define PWR_STATUS_MFG_2D BIT(22)
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@@ -59,6 +70,7 @@ enum clk_id {
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CLK_MFG,
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CLK_VENC,
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CLK_VENC_LT,
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+ CLK_ETHIF,
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CLK_MAX,
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};
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@@ -68,6 +80,7 @@ static const char * const clk_names[] =
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"mfg",
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"venc",
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"venc_lt",
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+ "ethif",
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NULL,
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};
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@@ -455,6 +468,96 @@ static void mtk_register_power_domains(s
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}
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/*
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+ * MT2701 power domain support
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+ */
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+
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+static const struct scp_domain_data scp_domain_data_mt2701[] = {
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+ [MT2701_POWER_DOMAIN_CONN] = {
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+ .name = "conn",
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+ .sta_mask = PWR_STATUS_CONN,
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+ .ctl_offs = SPM_CONN_PWR_CON,
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+ .bus_prot_mask = 0x0104,
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+ .clk_id = {CLK_NONE},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_DISP] = {
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+ .name = "disp",
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+ .sta_mask = PWR_STATUS_DISP,
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+ .ctl_offs = SPM_DIS_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .clk_id = {CLK_MM},
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+ .bus_prot_mask = 0x0002,
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_VDEC] = {
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+ .name = "vdec",
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+ .sta_mask = PWR_STATUS_VDEC,
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+ .ctl_offs = SPM_VDE_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(12, 12),
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+ .clk_id = {CLK_MM},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_ISP] = {
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+ .name = "isp",
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+ .sta_mask = PWR_STATUS_ISP,
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+ .ctl_offs = SPM_ISP_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(13, 12),
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+ .clk_id = {CLK_MM},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_BDP] = {
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+ .name = "bdp",
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+ .sta_mask = PWR_STATUS_BDP,
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+ .ctl_offs = SPM_BDP_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .clk_id = {CLK_NONE},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_ETH] = {
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+ .name = "eth",
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+ .sta_mask = PWR_STATUS_ETH,
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+ .ctl_offs = SPM_ETH_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_ETHIF},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_HIF] = {
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+ .name = "hif",
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+ .sta_mask = PWR_STATUS_HIF,
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+ .ctl_offs = SPM_HIF_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_ETHIF},
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+ .active_wakeup = true,
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+ },
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+ [MT2701_POWER_DOMAIN_IFR_MSC] = {
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+ .name = "ifr_msc",
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+ .sta_mask = PWR_STATUS_IFR_MSC,
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+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
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+ .clk_id = {CLK_NONE},
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+ .active_wakeup = true,
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+ },
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+};
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+
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+#define NUM_DOMAINS_MT2701 ARRAY_SIZE(scp_domain_data_mt2701)
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+
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+static int __init scpsys_probe_mt2701(struct platform_device *pdev)
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+{
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+ struct scp *scp;
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+
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+ scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
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+ if (IS_ERR(scp))
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+ return PTR_ERR(scp);
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+
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+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
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+
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+ return 0;
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+}
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+
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+/*
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* MT8173 power domain support
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*/
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@@ -583,6 +686,9 @@ static int __init scpsys_probe_mt8173(st
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static const struct of_device_id of_scpsys_match_tbl[] = {
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{
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+ .compatible = "mediatek,mt2701-scpsys",
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+ .data = scpsys_probe_mt2701,
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+ }, {
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.compatible = "mediatek,mt8173-scpsys",
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.data = scpsys_probe_mt8173,
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}, {
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