390 lines
12 KiB
Diff
390 lines
12 KiB
Diff
From 98830350d3fc824c1ff5c338140fe20f041a5916 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Wed, 6 Jul 2022 11:06:22 +0100
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Subject: [PATCH] nvmem: microchip-otpc: add support
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Add support for Microchip OTP controller available on SAMA7G5. The OTPC
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controls the access to a non-volatile memory. The memory behind OTPC is
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organized into packets, packets are composed by a fixed length header
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(4 bytes long) and a variable length payload (payload length is available
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in the header). When software request the data at an offset in memory
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the OTPC will return (via header + data registers) the whole packet that
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has a word at that offset. For the OTP memory layout like below:
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offset OTP Memory layout
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. .
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. ... .
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. .
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0x0E +-----------+ <--- packet X
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| header X |
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0x12 +-----------+
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| payload X |
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0x16 | |
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| |
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0x1A | |
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+-----------+
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. .
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. ... .
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. .
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if user requests data at address 0x16 the data started at 0x0E will be
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returned by controller. User will be able to fetch the whole packet
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starting at 0x0E (or parts of the packet) via proper registers. The same
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packet will be returned if software request the data at offset 0x0E or
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0x12 or 0x1A.
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The OTP will be populated by Microchip with at least 2 packets first one
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being boot configuration packet and the 2nd one being temperature
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calibration packet. The packet order will be preserved b/w different chip
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revisions but the packet sizes may change.
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For the above reasons and to keep the same software able to work on all
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chip variants the read function of the driver is working with a packet
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id instead of an offset in OTP memory.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Link: https://lore.kernel.org/r/20220706100627.6534-3-srinivas.kandagatla@linaro.org
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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MAINTAINERS | 8 +
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drivers/nvmem/Kconfig | 7 +
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drivers/nvmem/Makefile | 2 +
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drivers/nvmem/microchip-otpc.c | 288 +++++++++++++++++++++++++++++++++
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4 files changed, 305 insertions(+)
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create mode 100644 drivers/nvmem/microchip-otpc.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -11565,6 +11565,14 @@ S: Supported
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F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
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F: drivers/mtd/nand/raw/atmel/*
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+MICROCHIP OTPC DRIVER
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+M: Claudiu Beznea <claudiu.beznea@microchip.com>
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+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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+S: Supported
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+F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
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+F: drivers/nvmem/microchip-otpc.c
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+F: dt-bindings/nvmem/microchip,sama7g5-otpc.h
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+
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MICROCHIP PWM DRIVER
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M: Claudiu Beznea <claudiu.beznea@microchip.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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--- a/drivers/nvmem/Kconfig
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+++ b/drivers/nvmem/Kconfig
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@@ -107,6 +107,13 @@ config MTK_EFUSE
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This driver can also be built as a module. If so, the module
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will be called efuse-mtk.
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+config MICROCHIP_OTPC
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+ tristate "Microchip OTPC support"
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+ depends on ARCH_AT91 || COMPILE_TEST
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+ help
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+ This driver enable the OTP controller available on Microchip SAMA7G5
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+ SoCs. It controlls the access to the OTP memory connected to it.
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+
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config NVMEM_NINTENDO_OTP
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tristate "Nintendo Wii and Wii U OTP Support"
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depends on WII || COMPILE_TEST
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--- a/drivers/nvmem/Makefile
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+++ b/drivers/nvmem/Makefile
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@@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvm
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nvmem_sunplus_ocotp-y := sunplus-ocotp.o
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obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o
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nvmem-apple-efuses-y := apple-efuses.o
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+obj-$(CONFIG_MICROCHIP_OTPC) += nvmem-microchip-otpc.o
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+nvmem-microchip-otpc-y := microchip-otpc.o
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--- /dev/null
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+++ b/drivers/nvmem/microchip-otpc.c
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@@ -0,0 +1,288 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * OTP Memory controller
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+ *
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+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
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+ *
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+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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+ */
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+
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+#include <linux/bitfield.h>
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+#include <linux/iopoll.h>
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+#include <linux/module.h>
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+#include <linux/nvmem-provider.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+
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+#define MCHP_OTPC_CR (0x0)
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+#define MCHP_OTPC_CR_READ BIT(6)
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+#define MCHP_OTPC_MR (0x4)
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+#define MCHP_OTPC_MR_ADDR GENMASK(31, 16)
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+#define MCHP_OTPC_AR (0x8)
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+#define MCHP_OTPC_SR (0xc)
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+#define MCHP_OTPC_SR_READ BIT(6)
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+#define MCHP_OTPC_HR (0x20)
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+#define MCHP_OTPC_HR_SIZE GENMASK(15, 8)
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+#define MCHP_OTPC_DR (0x24)
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+
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+#define MCHP_OTPC_NAME "mchp-otpc"
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+#define MCHP_OTPC_SIZE (11 * 1024)
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+
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+/**
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+ * struct mchp_otpc - OTPC private data structure
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+ * @base: base address
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+ * @dev: struct device pointer
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+ * @packets: list of packets in OTP memory
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+ * @npackets: number of packets in OTP memory
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+ */
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+struct mchp_otpc {
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+ void __iomem *base;
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+ struct device *dev;
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+ struct list_head packets;
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+ u32 npackets;
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+};
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+
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+/**
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+ * struct mchp_otpc_packet - OTPC packet data structure
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+ * @list: list head
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+ * @id: packet ID
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+ * @offset: packet offset (in words) in OTP memory
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+ */
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+struct mchp_otpc_packet {
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+ struct list_head list;
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+ u32 id;
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+ u32 offset;
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+};
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+
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+static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
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+ u32 id)
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+{
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+ struct mchp_otpc_packet *packet;
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+
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+ if (id >= otpc->npackets)
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+ return NULL;
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+
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+ list_for_each_entry(packet, &otpc->packets, list) {
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+ if (packet->id == id)
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+ return packet;
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+ }
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+
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+ return NULL;
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+}
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+
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+static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
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+ unsigned int offset)
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+{
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+ u32 tmp;
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+
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+ /* Set address. */
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+ tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR);
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+ tmp &= ~MCHP_OTPC_MR_ADDR;
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+ tmp |= FIELD_PREP(MCHP_OTPC_MR_ADDR, offset);
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+ writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
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+
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+ /* Set read. */
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+ tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR);
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+ tmp |= MCHP_OTPC_CR_READ;
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+ writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR);
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+
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+ /* Wait for packet to be transferred into temporary buffers. */
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+ return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ),
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+ 10000, 2000, false, otpc->base + MCHP_OTPC_SR);
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+}
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+
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+/*
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+ * OTPC memory is organized into packets. Each packets contains a header and
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+ * a payload. Header is 4 bytes long and contains the size of the payload.
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+ * Payload size varies. The memory footprint is something as follows:
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+ *
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+ * Memory offset Memory footprint Packet ID
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+ * ------------- ---------------- ---------
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+ *
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+ * 0x0 +------------+ <-- packet 0
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+ * | header 0 |
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+ * 0x4 +------------+
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+ * | payload 0 |
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+ * . .
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+ * . ... .
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+ * . .
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+ * offset1 +------------+ <-- packet 1
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+ * | header 1 |
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+ * offset1 + 0x4 +------------+
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+ * | payload 1 |
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+ * . .
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+ * . ... .
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+ * . .
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+ * offset2 +------------+ <-- packet 2
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+ * . .
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+ * . ... .
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+ * . .
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+ * offsetN +------------+ <-- packet N
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+ * | header N |
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+ * offsetN + 0x4 +------------+
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+ * | payload N |
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+ * . .
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+ * . ... .
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+ * . .
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+ * +------------+
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+ *
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+ * where offset1, offset2, offsetN depends on the size of payload 0, payload 1,
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+ * payload N-1.
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+ *
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+ * The access to memory is done on a per packet basis: the control registers
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+ * need to be updated with an offset address (within a packet range) and the
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+ * data registers will be update by controller with information contained by
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+ * that packet. E.g. if control registers are updated with any address within
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+ * the range [offset1, offset2) the data registers are updated by controller
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+ * with packet 1. Header data is accessible though MCHP_OTPC_HR register.
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+ * Payload data is accessible though MCHP_OTPC_DR and MCHP_OTPC_AR registers.
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+ * There is no direct mapping b/w the offset requested by software and the
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+ * offset returned by hardware.
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+ *
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+ * For this, the read function will return the first requested bytes in the
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+ * packet. The user will have to be aware of the memory footprint before doing
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+ * the read request.
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+ */
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+static int mchp_otpc_read(void *priv, unsigned int off, void *val,
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+ size_t bytes)
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+{
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+ struct mchp_otpc *otpc = priv;
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+ struct mchp_otpc_packet *packet;
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+ u32 *buf = val;
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+ u32 offset;
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+ size_t len = 0;
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+ int ret, payload_size;
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+
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+ /*
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+ * We reach this point with off being multiple of stride = 4 to
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+ * be able to cross the subsystem. Inside the driver we use continuous
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+ * unsigned integer numbers for packet id, thus devide off by 4
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+ * before passing it to mchp_otpc_id_to_packet().
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+ */
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+ packet = mchp_otpc_id_to_packet(otpc, off / 4);
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+ if (!packet)
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+ return -EINVAL;
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+ offset = packet->offset;
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+
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+ while (len < bytes) {
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+ ret = mchp_otpc_prepare_read(otpc, offset);
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+ if (ret)
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+ return ret;
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+
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+ /* Read and save header content. */
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+ *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_HR);
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+ len += sizeof(*buf);
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+ offset++;
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+ if (len >= bytes)
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+ break;
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+
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+ /* Read and save payload content. */
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+ payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1));
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+ writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR);
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+ do {
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+ *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR);
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+ len += sizeof(*buf);
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+ offset++;
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+ payload_size--;
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+ } while (payload_size >= 0 && len < bytes);
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+ }
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+
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+ return 0;
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+}
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+
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+static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
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+{
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+ struct mchp_otpc_packet *packet;
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+ u32 word, word_pos = 0, id = 0, npackets = 0, payload_size;
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+ int ret;
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+
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+ INIT_LIST_HEAD(&otpc->packets);
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+ *size = 0;
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+
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+ while (*size < MCHP_OTPC_SIZE) {
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+ ret = mchp_otpc_prepare_read(otpc, word_pos);
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+ if (ret)
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+ return ret;
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+
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+ word = readl_relaxed(otpc->base + MCHP_OTPC_HR);
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+ payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, word);
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+ if (!payload_size)
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+ break;
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+
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+ packet = devm_kzalloc(otpc->dev, sizeof(*packet), GFP_KERNEL);
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+ if (!packet)
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+ return -ENOMEM;
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+
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+ packet->id = id++;
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+ packet->offset = word_pos;
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+ INIT_LIST_HEAD(&packet->list);
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+ list_add_tail(&packet->list, &otpc->packets);
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+
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+ /* Count size by adding header and paload sizes. */
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+ *size += 4 * (payload_size + 1);
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+ /* Next word: this packet (header, payload) position + 1. */
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+ word_pos += payload_size + 2;
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+
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+ npackets++;
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+ }
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+
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+ otpc->npackets = npackets;
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+
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+ return 0;
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+}
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+
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+static struct nvmem_config mchp_nvmem_config = {
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+ .name = MCHP_OTPC_NAME,
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+ .type = NVMEM_TYPE_OTP,
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+ .read_only = true,
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+ .word_size = 4,
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+ .stride = 4,
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+ .reg_read = mchp_otpc_read,
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+};
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+
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+static int mchp_otpc_probe(struct platform_device *pdev)
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+{
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+ struct nvmem_device *nvmem;
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+ struct mchp_otpc *otpc;
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+ u32 size;
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+ int ret;
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+
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+ otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL);
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+ if (!otpc)
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+ return -ENOMEM;
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+
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+ otpc->base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(otpc->base))
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+ return PTR_ERR(otpc->base);
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+
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+ otpc->dev = &pdev->dev;
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+ ret = mchp_otpc_init_packets_list(otpc, &size);
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+ if (ret)
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+ return ret;
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+
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+ mchp_nvmem_config.dev = otpc->dev;
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+ mchp_nvmem_config.size = size;
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+ mchp_nvmem_config.priv = otpc;
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+ nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
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+
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+ return PTR_ERR_OR_ZERO(nvmem);
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+}
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+
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+static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
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+ { .compatible = "microchip,sama7g5-otpc", },
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+ { },
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+};
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+MODULE_DEVICE_TABLE(of, mchp_otpc_ids);
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+
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+static struct platform_driver mchp_otpc_driver = {
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+ .probe = mchp_otpc_probe,
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+ .driver = {
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+ .name = MCHP_OTPC_NAME,
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+ .of_match_table = of_match_ptr(mchp_otpc_ids),
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+ },
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+};
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+module_platform_driver(mchp_otpc_driver);
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+
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+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea@microchip.com>");
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+MODULE_DESCRIPTION("Microchip SAMA7G5 OTPC driver");
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+MODULE_LICENSE("GPL");
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