b1f21329d4
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. It shares most of the stuff with its external counterpart, however it is modified for the SoC. Namely, it doesn't have second CPU port (Port 6), so it has 6 ports instead of 7. It also has no built-in PHY-s but rather requires external PSGMII based companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry out calibration before using them. PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which unfortunately requires some magic values as the datasheet doesnt document the bits that are being set or the register at all. Since its built-in it is MMIO like other peripherals and doesn't have its own MDIO bus but depends on the SoC provided one. CPU connection is at Port 0 and it uses some kind of a internal connection and no traditional RGMII/SGMII. It also doesn't use in-band tagging like other qca8k switches so a shinfo based tagger is used. This is based on the current OpenWrt qca8k version that has been imported from generic target. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
99 lines
2.1 KiB
Diff
99 lines
2.1 KiB
Diff
From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Mon, 1 Nov 2021 18:15:04 +0100
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Subject: [PATCH] arm: dts: ipq4019: add switch node
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Since the built-in IPQ40xx switch now has a driver, add the required node
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for it to work.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
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1 file changed, 78 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -590,6 +590,82 @@
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status = "disabled";
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};
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+ switch: switch@c000000 {
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+ compatible = "qca,ipq4019-qca8337n";
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+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
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+ reg-names = "base", "psgmii_phy";
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+ resets = <&gcc ESS_PSGMII_ARES>;
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+ reset-names = "psgmii_rst";
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+ mdio = <&mdio>;
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+ psgmii-ethphy = <&psgmiiphy>;
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+
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 { /* MAC0 */
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+ reg = <0>;
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+ label = "cpu";
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+ ethernet = <&gmac>;
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+ phy-mode = "internal";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ asym-pause;
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+ };
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+ };
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+
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+ swport1: port@1 { /* MAC1 */
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+ reg = <1>;
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+ label = "lan1";
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+ phy-handle = <ðphy0>;
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+ phy-mode = "psgmii";
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+
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+ status = "disabled";
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+ };
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+
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+ swport2: port@2 { /* MAC2 */
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+ reg = <2>;
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+ label = "lan2";
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+ phy-handle = <ðphy1>;
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+ phy-mode = "psgmii";
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+
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+ status = "disabled";
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+ };
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+
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+ swport3: port@3 { /* MAC3 */
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+ reg = <3>;
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+ label = "lan3";
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+ phy-handle = <ðphy2>;
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+ phy-mode = "psgmii";
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+
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+ status = "disabled";
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+ };
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+
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+ swport4: port@4 { /* MAC4 */
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+ reg = <4>;
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+ label = "lan4";
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+ phy-handle = <ðphy3>;
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+ phy-mode = "psgmii";
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+
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+ status = "disabled";
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+ };
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+
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+ swport5: port@5 { /* MAC5 */
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+ reg = <5>;
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+ label = "wan";
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+ phy-handle = <ðphy4>;
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+ phy-mode = "psgmii";
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+
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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gmac: ethernet@c080000 {
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compatible = "qcom,ipq4019-ess-edma";
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reg = <0xc080000 0x8000>;
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