f584fb2f7e
Import some accepted and pending upstream patches for mtk_eth_soc, replacing some semantically equivalent local patches and fixing issues when operating the PCS in 1G SGMII mode. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From b66105968b8c37c26a75b9da9281cbc1c8f73594 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 22 Jan 2023 23:58:36 +0000
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Subject: [PATCH] net: ethernet: mtk_eth_soc: reset PCS state
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Reset PCS state when changing interface mode.
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Tested-by: Bjørn Mork <bjorn@mork.no>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++++
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2 files changed, 8 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -504,6 +504,10 @@
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#define SGMII_SEND_AN_ERROR_EN BIT(11)
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#define SGMII_IF_MODE_MASK GENMASK(5, 1)
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+/* Register to reset SGMII design */
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+#define SGMII_RESERVED_0 0x34
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+#define SGMII_SW_RESET BIT(0)
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+
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/* Register to set SGMII speed, ANA RG_ Control Signals III*/
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#define SGMSYS_ANA_RG_CS3 0x2028
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#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -86,6 +86,10 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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+ /* Reset SGMII PCS state */
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+ regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
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+ SGMII_SW_RESET, SGMII_SW_RESET);
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+
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mpcs->interface = interface;
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}
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