b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
29 lines
1.2 KiB
Diff
29 lines
1.2 KiB
Diff
From a19df563230af392f2e84e57d69367f96b4a8c56 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 12 Jul 2022 16:42:43 +0200
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Subject: [PATCH] arm64: dts: qcom: align SDHCI reg-names with DT schema
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DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
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just like TXT bindings were expecting before the conversion.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220712144245.17417-4-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -383,7 +383,7 @@
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sdhc_1: mmc@7824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x7824900 0x500>, <0x7824000 0x800>;
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- reg-names = "hc_mem", "core_mem";
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+ reg-names = "hc", "core";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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