e7bfda2c24
This change makes the names of Broadcom targets consistent by using the common notation based on SoC/CPU ID (which is used internally anyway), bcmXXXX instead of brcmXXXX. This is even used for target TITLE in make menuconfig already, only the short target name used brcm so far. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
107 lines
2.8 KiB
Diff
107 lines
2.8 KiB
Diff
From 28cc80e4ada5d73d5305fd268297825cd8d01936 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Wed, 27 Jul 2016 11:37:08 +0200
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Subject: [PATCH 12/16] Documentation: add BCM63268 pincontroller binding
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documentation
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Add binding documentation for the pincontrol core found in the BCM63268
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family SoCs.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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.../bindings/pinctrl/brcm,bcm63268-pinctrl.txt | 88 ++++++++++++++++++++++
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1 file changed, 88 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt
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@@ -0,0 +1,88 @@
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+* Broadcom BCM63268 pin controller
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+
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+Required properties:
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+- compatible: Must be "brcm,bcm6362-pinctrl".
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+- reg: Register specifiers of dirout, dat, led, mode, ctrl, basemode registers.
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+- reg-names: Must be "dirout", "dat", "led", "mode", "ctrl", "basemode".
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+- gpio-controller: Identifies this node as a GPIO controller.
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+- #gpio-cells: Must be <2>.
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+
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+Example:
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+
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+pinctrl: pin-controller@100000c0 {
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+ compatible = "brcm,bcm63268-pinctrl";
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+ reg = <0x100000c0 0x8>,
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+ <0x100000c8 0x8>,
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+ <0x100000d0 0x4>,
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+ <0x100000d8 0x4>,
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+ <0x100000dc 0x4>,
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+ <0x100000f8 0x4>;
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+ reg-names = "dirout", "dat", "led", "mode",
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+ "ctrl", "basemode";
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+};
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+
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+Available pins/groups and functions:
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+
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+name pins functions
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+-----------------------------------------------------------
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+gpio0 0 led, serial_led_clk
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+gpio1 1 led, serial_led_data
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+gpio2 2 led,
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+gpio3 3 led,
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+gpio4 4 led,
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+gpio5 5 led,
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+gpio6 6 led,
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+gpio7 7 led,
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+gpio8 8 led, hsspi_cs6
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+gpio9 9 led, hsspi_cs7
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+gpio10 10 led, uart1_scts
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+gpio11 11 led, uart1_srts
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+gpio12 12 led, uart1_sdin
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+gpio13 13 led, uart1_sdout
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+gpio14 14 led, ntr_pulse_in
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+gpio15 15 led, dsl_ntr_pulse_out
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+gpio16 16 led, hsspi_cs4
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+gpio17 17 led, hsspi_cs5
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+gpio18 18 led, adsl_spi_miso
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+gpio19 19 led, adsl_spi_mosi
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+gpio20 20 led,
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+gpio21 21 led,
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+gpio22 22 led, vreg_clk
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+gpio23 23 led, pcie_clkreq_b
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+gpio24 24 uart1_scts
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+gpio25 25 uart1_srts
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+gpio26 26 uart1_sdin
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+gpio27 27 uart1_sdout
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+gpio28 28 ntr_pulse_in
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+gpio29 29 dsl_ntr_pulse_out
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+gpio30 30 switch_led_clk
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+gpio31 31 switch_led_data
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+gpio32 32 wifi
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+gpio33 33 wifi
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+gpio34 34 wifi
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+gpio35 35 wifi
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+gpio36 36 wifi
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+gpio37 37 wifi
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+gpio38 38 wifi
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+gpio39 39 wifi
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+gpio40 40 wifi
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+gpio41 41 wifi
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+gpio42 42 wifi
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+gpio43 43 wifi
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+gpio44 44 wifi
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+gpio45 45 wifi
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+gpio46 46 wifi
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+gpio47 47 wifi
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+gpio48 48 wifi
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+gpio49 49 wifi
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+gpio50 50 wifi
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+gpio51 51 wifi
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+nand_grp 2-7,24-31 nand
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+dect_pd_grp 8-9 dect_pd
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+vdsl_phy0_grp 10-11 vdsl_phy0
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+vdsl_phy1_grp 12-13 vdsl_phy1
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+vdsl_phy2_grp 24-25 vdsl_phy2
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+vdsl_phy3_grp 26-27 vdsl_phy3
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