9a417fbd0d
Refreshed all patches. Compile-tested on: ipq40xx, ramips Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
86 lines
2.9 KiB
Diff
86 lines
2.9 KiB
Diff
From 3c6b94d7091f0793445f2faf777e584af643e9da Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:36 +0800
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Subject: [PATCH 157/224] mmc: mediatek: add support of source_cg clock
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source clock need an independent cg to control, when doing clk mode
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switch, need gate source clock to avoid hw issue(multi-bit sync hw hang)
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 23 ++++++++++++++++++++++-
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1 file changed, 22 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -374,6 +374,7 @@ struct msdc_host {
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struct clk *src_clk; /* msdc source clock */
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struct clk *h_clk; /* msdc h_clk */
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+ struct clk *src_clk_cg; /* msdc source clock control gate */
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u32 mclk; /* mmc subsystem clock frequency */
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u32 src_clk_freq; /* source clock frequency */
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u32 sclk; /* SD/MS bus clock frequency */
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@@ -618,6 +619,7 @@ static void msdc_set_timeout(struct msdc
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static void msdc_gate_clock(struct msdc_host *host)
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{
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+ clk_disable_unprepare(host->src_clk_cg);
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clk_disable_unprepare(host->src_clk);
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clk_disable_unprepare(host->h_clk);
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}
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@@ -626,6 +628,7 @@ static void msdc_ungate_clock(struct msd
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{
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clk_prepare_enable(host->h_clk);
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clk_prepare_enable(host->src_clk);
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+ clk_prepare_enable(host->src_clk_cg);
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while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
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cpu_relax();
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}
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@@ -694,6 +697,15 @@ static void msdc_set_mclk(struct msdc_ho
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sclk = (host->src_clk_freq >> 2) / div;
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}
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}
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+ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
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+ /*
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+ * As src_clk/HCLK use the same bit to gate/ungate,
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+ * So if want to only gate src_clk, need gate its parent(mux).
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+ */
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+ if (host->src_clk_cg)
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+ clk_disable_unprepare(host->src_clk_cg);
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+ else
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+ clk_disable_unprepare(clk_get_parent(host->src_clk));
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if (host->dev_comp->clk_div_bits == 8)
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sdr_set_field(host->base + MSDC_CFG,
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MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
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@@ -702,10 +714,14 @@ static void msdc_set_mclk(struct msdc_ho
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sdr_set_field(host->base + MSDC_CFG,
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MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
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(mode << 12) | div);
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+ if (host->src_clk_cg)
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+ clk_prepare_enable(host->src_clk_cg);
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+ else
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+ clk_prepare_enable(clk_get_parent(host->src_clk));
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- sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
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while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
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cpu_relax();
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+ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
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host->sclk = sclk;
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host->mclk = hz;
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host->timing = timing;
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@@ -1825,6 +1841,11 @@ static int msdc_drv_probe(struct platfor
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goto host_free;
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}
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+ /*source clock control gate is optional clock*/
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+ host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
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+ if (IS_ERR(host->src_clk_cg))
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+ host->src_clk_cg = NULL;
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+
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host->irq = platform_get_irq(pdev, 0);
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if (host->irq < 0) {
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ret = -EINVAL;
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