afd4bf08bc
Manually merged:
layerscape/808-i2c-0011-i2c-imx-support-slave-mode-for-imx-I2C-driver.patch
layerscape/808-i2c-0012-i2c-imx-correct-code-of-errata-A-010650-for-layersca.patch
Remaining modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711, x86/64 [*],
ramips/mt7621 [*], ath79/tiny [*], ipq40xx [*], octeon [*],
realtek [*]
Run-tested: ipq806x/R7800, ramips/mt7621 [*], octeon [*], realtek [*]
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Tested-by: Stijn Segers <foss@volatilesystems.org> [*]
95 lines
3.1 KiB
Diff
95 lines
3.1 KiB
Diff
From ede2da5ea630fa2431145992c43aef51fc9c5c5a Mon Sep 17 00:00:00 2001
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From: Clark Wang <xiaoning.wang@nxp.com>
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Date: Fri, 18 Jan 2019 12:00:16 +0800
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Subject: [PATCH] MLK-20773 i2c-imx: add a limit of maximum transfer speed for
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imx7d
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According the e7805 in Errata, the SCK low level period should be less
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than 1.3us.
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The other series platform use this same IP can match the errata, and
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ensure the low level period longer than 1.3us when the speed set to
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400KHz. However, only at imx7d platform, the low level period is less
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than 1.3us in the same situation.
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Therefore, limit the maximum transfer speed to 384KHz when probe at
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imx7d platform.
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Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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(cherry picked from commit 19f553846e872b5c379b37ed029132b79566cab0)
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(cherry picked from commit 5d355407812025e5157f82b7763580e7295a40fd)
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---
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drivers/i2c/busses/i2c-imx.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/drivers/i2c/busses/i2c-imx.c
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+++ b/drivers/i2c/busses/i2c-imx.c
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@@ -51,6 +51,7 @@
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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+#define IMX_I2C_MAX_E_BIT_RATE 384000 /* 384kHz from e7805 errata*/
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/*
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* Enable DMA if transfer byte size is bigger than this threshold.
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@@ -161,6 +162,7 @@ enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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VF610_I2C,
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+ IMX7D_I2C,
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};
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struct imx_i2c_hwdata {
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@@ -235,6 +237,16 @@ static struct imx_i2c_hwdata vf610_i2c_h
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};
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+static const struct imx_i2c_hwdata imx7d_i2c_hwdata = {
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+ .devtype = IMX7D_I2C,
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+ .regshift = IMX_I2C_REGSHIFT,
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+ .clk_div = imx_i2c_clk_div,
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+ .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
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+ .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
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+ .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
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+
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+};
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+
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static const struct platform_device_id imx_i2c_devtype[] = {
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{
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.name = "imx1-i2c",
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@@ -252,6 +264,7 @@ static const struct of_device_id i2c_imx
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{ .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
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{ .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
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{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
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+ { .compatible = "fsl,imx7d-i2c", .data = &imx7d_i2c_hwdata, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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@@ -267,6 +280,11 @@ static inline int is_imx1_i2c(struct imx
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return i2c_imx->hwdata->devtype == IMX1_I2C;
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}
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+static inline int is_imx7d_i2c(struct imx_i2c_struct *i2c_imx)
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+{
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+ return i2c_imx->hwdata->devtype == IMX7D_I2C;
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+}
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+
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static inline void imx_i2c_write_reg(unsigned int val,
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struct imx_i2c_struct *i2c_imx, unsigned int reg)
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{
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@@ -1187,6 +1205,14 @@ static int i2c_imx_probe(struct platform
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clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
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i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
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+ /*
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+ * This limit caused by an i.MX7D hardware issue(e7805 in Errata).
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+ * If there is no limit, when the bitrate set up to 400KHz, it will
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+ * cause the SCK low level period less than 1.3us.
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+ */
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+ if (is_imx7d_i2c(i2c_imx) && i2c_imx->bitrate > IMX_I2C_MAX_E_BIT_RATE)
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+ i2c_imx->bitrate = IMX_I2C_MAX_E_BIT_RATE;
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+
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/* Set up chip registers to defaults */
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imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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i2c_imx, IMX_I2C_I2CR);
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