e08942e76a
All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia <graysky@archlinux.us>
61 lines
1.7 KiB
Diff
61 lines
1.7 KiB
Diff
From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Wed, 9 Dec 2020 15:03:35 +0200
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Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure
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Unprepare clocks in case of any failure in fu540_c000_clk_init().
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Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000")
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------
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1 file changed, 18 insertions(+), 6 deletions(-)
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--- a/drivers/net/ethernet/cadence/macb_main.c
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+++ b/drivers/net/ethernet/cadence/macb_main.c
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@@ -4338,8 +4338,10 @@ static int fu540_c000_clk_init(struct pl
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return err;
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mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
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- if (!mgmt)
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- return -ENOMEM;
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+ if (!mgmt) {
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+ err = -ENOMEM;
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+ goto err_disable_clks;
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+ }
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init.name = "sifive-gemgxl-mgmt";
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init.ops = &fu540_c000_ops;
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@@ -4350,16 +4352,26 @@ static int fu540_c000_clk_init(struct pl
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mgmt->hw.init = &init;
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*tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
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- if (IS_ERR(*tx_clk))
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- return PTR_ERR(*tx_clk);
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+ if (IS_ERR(*tx_clk)) {
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+ err = PTR_ERR(*tx_clk);
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+ goto err_disable_clks;
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+ }
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err = clk_prepare_enable(*tx_clk);
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- if (err)
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+ if (err) {
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dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
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- else
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+ *tx_clk = NULL;
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+ goto err_disable_clks;
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+ } else {
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dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
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+ }
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return 0;
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+
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+err_disable_clks:
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+ macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
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+
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+ return err;
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}
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static int fu540_c000_init(struct platform_device *pdev)
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