6be0da90a1
Removed upstreamed/solved elsewhere upstream: - 0001-MIPS-ralink-Add-rt3352-SPI_CS1-pinmux.patch - 0002-MIPS-pci-rt2880-set-pci-controller-of_node.patch - 0004-MIPS-ralink-add-MT7621-pcie-driver.patch - 0009-PCI-MIPS-enable-PCIe-on-MT7688.patch - 0025-pinctrl-ralink-add-pinctrl-driver.patch - 0028-GPIO-ralink-add-mt7621-gpio-controller.patch - 0043-spi-add-mt7621-support.patch - 0045-i2c-add-mt7621-driver.patch - 0047-DMA-ralink-add-rt2880-dma-engine.patch - 0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch - 0054-mtd-spi-nor-w25q256-respect-default-mode.patch - 0099-pci-mt7620.patch - 304-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch Removed because of the new NAND driver: - 0038-Revert-mtd-nand-Remove-unused-chip-write_page-hook.patch - 0039-mtd-add-mt7621-nand-support.patch - 0040-nand-hack.patch Remove patch that no longer applies (needs rework): - 0034-NET-multi-phy-support.patch Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
88 lines
1.9 KiB
Diff
88 lines
1.9 KiB
Diff
--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -7,6 +7,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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+#include <linux/jiffies.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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@@ -14,6 +15,7 @@
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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#include <asm/mips-boards/launch.h>
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+#include <asm/delay.h>
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#include <pinmux.h>
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@@ -175,6 +177,58 @@ bool plat_cpu_core_present(int core)
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return true;
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}
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+#define LPS_PREC 8
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+/*
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+* Re-calibration lpj(loop-per-jiffy).
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+* (derived from kernel/calibrate.c)
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+*/
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+static int udelay_recal(void)
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+{
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+ unsigned int i, lpj = 0;
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+ unsigned long ticks, loopbit;
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+ int lps_precision = LPS_PREC;
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+
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+ lpj = (1<<12);
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+
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+ while ((lpj <<= 1) != 0) {
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+ /* wait for "start of" clock tick */
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+ ticks = jiffies;
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+ while (ticks == jiffies)
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+ /* nothing */;
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+
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+ /* Go .. */
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+ ticks = jiffies;
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+ __delay(lpj);
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+ ticks = jiffies - ticks;
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+ if (ticks)
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+ break;
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+ }
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+
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+ /*
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+ * Do a binary approximation to get lpj set to
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+ * equal one clock (up to lps_precision bits)
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+ */
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+ lpj >>= 1;
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+ loopbit = lpj;
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+ while (lps_precision-- && (loopbit >>= 1)) {
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+ lpj |= loopbit;
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+ ticks = jiffies;
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+ while (ticks == jiffies)
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+ /* nothing */;
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+ ticks = jiffies;
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+ __delay(lpj);
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+ if (jiffies != ticks) /* longer than 1 tick */
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+ lpj &= ~loopbit;
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+ }
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+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
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+
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+ for(i=0; i< NR_CPUS; i++)
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+ cpu_data[i].udelay_val = lpj;
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+
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+ return 0;
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+}
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+device_initcall(udelay_recal);
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+
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -58,6 +58,7 @@ choice
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select CLKSRC_MIPS_GIC
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select HAVE_PCI if PCI_MT7621
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select WEAK_REORDERING_BEYOND_LLSC
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+ select GENERIC_CLOCKEVENTS_BROADCAST
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endchoice
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choice
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