4ebec0b3e2
All modification by update_kernel.sh.
Build system: x86_64
Build-tested: ipq806x/R7800, bcm27xx/bcm2711
Run-tested: ipq806x/R7800
No dmesg regressions, everything functional
Compile-tested [*]: ath79/{generic,tiny}, ipq40xx, octeon,
ramips/mt7621, realtek, x86/64.
Run-tested [*]: ramips/mt7621 (DIR-878 A1, R6800, RT-AC57U),
octeon (EdgeRouter Lite).
Signed-off-by: John Audia <graysky@archlinux.us>
Tested-by: Stijn Segers <foss@volatilesystems.org> [*]
30 lines
890 B
Diff
30 lines
890 B
Diff
From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:15:32 +0100
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Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/kernel/setup.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/kernel/setup.c
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+++ b/arch/mips/kernel/setup.c
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@@ -723,8 +723,6 @@ static void __init arch_mem_init(char **
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memblock_reserve(crashk_res.start,
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crashk_res.end - crashk_res.start + 1);
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#endif
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- device_tree_init();
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-
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/*
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* In order to reduce the possibility of kernel panic when failed to
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* get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate
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@@ -841,6 +839,7 @@ void __init setup_arch(char **cmdline_p)
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cpu_cache_init();
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paging_init();
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+ device_tree_init();
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}
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unsigned long kernelsp[NR_CPUS];
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