ddcebda08b
Add kernel tag that introduced the patch on backport patch. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
165 lines
4.4 KiB
Diff
165 lines
4.4 KiB
Diff
From 2481d206fae7884cd07014fd1318e63af35e99eb Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Wed, 2 Feb 2022 01:03:33 +0100
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Subject: [PATCH 14/16] net: dsa: qca8k: cache lo and hi for mdio write
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From Documentation, we can cache lo and hi the same way we do with the
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page. This massively reduce the mdio write as 3/4 of the time as we only
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require to write the lo or hi part for a mdio write.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++++++++--------
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drivers/net/dsa/qca8k.h | 5 ++++
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2 files changed, 54 insertions(+), 12 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -89,6 +89,44 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
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}
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static int
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+qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
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+{
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+ u16 *cached_lo = &priv->mdio_cache.lo;
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+ struct mii_bus *bus = priv->bus;
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+ int ret;
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+
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+ if (lo == *cached_lo)
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+ return 0;
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+
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+ ret = bus->write(bus, phy_id, regnum, lo);
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+ if (ret < 0)
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to write qca8k 32bit lo register\n");
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+
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+ *cached_lo = lo;
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+ return 0;
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+}
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+
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+static int
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+qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
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+{
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+ u16 *cached_hi = &priv->mdio_cache.hi;
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+ struct mii_bus *bus = priv->bus;
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+ int ret;
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+
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+ if (hi == *cached_hi)
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+ return 0;
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+
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+ ret = bus->write(bus, phy_id, regnum, hi);
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+ if (ret < 0)
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to write qca8k 32bit hi register\n");
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+
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+ *cached_hi = hi;
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+ return 0;
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+}
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+
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+static int
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qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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{
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int ret;
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@@ -111,7 +149,7 @@ qca8k_mii_read32(struct mii_bus *bus, in
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}
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static void
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-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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+qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
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{
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u16 lo, hi;
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int ret;
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@@ -119,12 +157,9 @@ qca8k_mii_write32(struct mii_bus *bus, i
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lo = val & 0xffff;
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hi = (u16)(val >> 16);
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- ret = bus->write(bus, phy_id, regnum, lo);
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+ ret = qca8k_set_lo(priv, phy_id, regnum, lo);
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if (ret >= 0)
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- ret = bus->write(bus, phy_id, regnum + 1, hi);
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- if (ret < 0)
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- dev_err_ratelimited(&bus->dev,
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- "failed to write qca8k 32bit register\n");
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+ ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
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}
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static int
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@@ -400,7 +435,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
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if (ret < 0)
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goto exit;
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- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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@@ -433,7 +468,7 @@ qca8k_regmap_update_bits(void *ctx, uint
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val &= ~mask;
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val |= write_val;
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- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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@@ -1117,14 +1152,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
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if (ret)
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goto exit;
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- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
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mutex_unlock(&bus->mdio_lock);
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@@ -1154,7 +1189,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
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if (ret)
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goto exit;
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- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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@@ -1165,7 +1200,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
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+ qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
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mutex_unlock(&bus->mdio_lock);
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@@ -3057,6 +3092,8 @@ qca8k_sw_probe(struct mdio_device *mdiod
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}
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priv->mdio_cache.page = 0xffff;
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+ priv->mdio_cache.lo = 0xffff;
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+ priv->mdio_cache.hi = 0xffff;
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/* Check the detected switch id */
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ret = qca8k_read_switch_id(priv);
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -369,6 +369,11 @@ struct qca8k_mdio_cache {
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* mdio writes
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*/
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u16 page;
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+/* lo and hi can also be cached and from Documentation we can skip one
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+ * extra mdio write if lo or hi is didn't change.
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+ */
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+ u16 lo;
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+ u16 hi;
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};
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struct qca8k_priv {
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