c0683ec458
This commit fixes the following commit
f584fb2f7e kernel: import accepted MediaTek Ethernet patches
Unrefreshed patches caused the CI to fail.
Signed-off-by: Paul Spooren <mail@aparcar.org>
45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From b66105968b8c37c26a75b9da9281cbc1c8f73594 Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Sun, 22 Jan 2023 23:58:36 +0000
|
|
Subject: [PATCH] net: ethernet: mtk_eth_soc: reset PCS state
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Reset PCS state when changing interface mode.
|
|
|
|
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
Tested-by: Bjørn Mork <bjorn@mork.no>
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
|
|
drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++++
|
|
2 files changed, 8 insertions(+)
|
|
|
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
@@ -529,6 +529,10 @@
|
|
#define SGMII_SEND_AN_ERROR_EN BIT(11)
|
|
#define SGMII_IF_MODE_MASK GENMASK(5, 1)
|
|
|
|
+/* Register to reset SGMII design */
|
|
+#define SGMII_RESERVED_0 0x34
|
|
+#define SGMII_SW_RESET BIT(0)
|
|
+
|
|
/* Register to set SGMII speed, ANA RG_ Control Signals III*/
|
|
#define SGMSYS_ANA_RG_CS3 0x2028
|
|
#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
|
|
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
@@ -90,6 +90,10 @@ static int mtk_pcs_config(struct phylink
|
|
regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
|
|
SGMII_PHYA_PWD, SGMII_PHYA_PWD);
|
|
|
|
+ /* Reset SGMII PCS state */
|
|
+ regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
|
|
+ SGMII_SW_RESET, SGMII_SW_RESET);
|
|
+
|
|
mpcs->interface = interface;
|
|
}
|
|
|