b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
26 lines
886 B
Diff
26 lines
886 B
Diff
From f5441c669d5442d247c69bab3eb27c074c0dd19a Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robimarko@gmail.com>
|
|
Date: Sun, 15 May 2022 23:00:45 +0200
|
|
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add USB GDSCs
|
|
|
|
Add bindings for the USB GDSCs found in IPQ8074 GCC.
|
|
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com
|
|
---
|
|
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++
|
|
1 file changed, 3 insertions(+)
|
|
|
|
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
@@ -368,4 +368,7 @@
|
|
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
|
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
|
|
|
+#define USB0_GDSC 0
|
|
+#define USB1_GDSC 1
|
|
+
|
|
#endif
|