7d7aa2fd92
This change makes the names of Broadcom targets consistent by using the common notation based on SoC/CPU ID (which is used internally anyway), bcmXXXX instead of brcmXXXX. This is even used for target TITLE in make menuconfig already, only the short target name used brcm so far. Despite, since subtargets range from bcm2708 to bcm2711, it seems appropriate to use bcm27xx instead of bcm2708 (again, as already done for BOARDNAME). This also renames the packages brcm2708-userland and brcm2708-gpu-fw. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
From a7ca69081e7d0e1c5d84352c219b454a7977a2a4 Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Fri, 25 Aug 2017 19:18:13 +0100
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Subject: [PATCH] cache: export clean and invalidate
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---
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arch/arm/mm/cache-v6.S | 4 ++--
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arch/arm/mm/cache-v7.S | 4 ++--
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2 files changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/arm/mm/cache-v6.S
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+++ b/arch/arm/mm/cache-v6.S
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@@ -201,7 +201,7 @@ ENTRY(v6_flush_kern_dcache_area)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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-v6_dma_inv_range:
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+ENTRY(v6_dma_inv_range)
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#ifdef CONFIG_DMA_CACHE_RWFO
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ldrb r2, [r0] @ read for ownership
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strb r2, [r0] @ write for ownership
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@@ -246,7 +246,7 @@ v6_dma_inv_range:
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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-v6_dma_clean_range:
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+ENTRY(v6_dma_clean_range)
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bic r0, r0, #D_CACHE_LINE_SIZE - 1
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1:
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#ifdef CONFIG_DMA_CACHE_RWFO
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--- a/arch/arm/mm/cache-v7.S
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+++ b/arch/arm/mm/cache-v7.S
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@@ -350,7 +350,7 @@ ENDPROC(v7_flush_kern_dcache_area)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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-v7_dma_inv_range:
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+ENTRY(v7_dma_inv_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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tst r0, r3
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@@ -380,7 +380,7 @@ ENDPROC(v7_dma_inv_range)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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-v7_dma_clean_range:
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+ENTRY(v7_dma_clean_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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