 cddd459140
			
		
	
	cddd459140
	
	
	
		
			
			Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
		
			
				
	
	
		
			111 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			111 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From 8464c7b6e7c491ae06b18103881611c98678cf1f Mon Sep 17 00:00:00 2001
 | |
| From: Haiying Wang <Haiying.Wang@nxp.com>
 | |
| Date: Thu, 13 Apr 2017 14:54:01 -0400
 | |
| Subject: [PATCH] soc: fsl: dpio: enable qbman CENA portal memory access
 | |
| 
 | |
| Once we enable the cacheable portal memory, we need to do
 | |
| cache flush for enqueue, vdq, buffer release, and management
 | |
| commands, as well as invalidate and prefetch for the valid bit
 | |
| of management command response and next index of dqrr.
 | |
| 
 | |
| Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
 | |
| ---
 | |
|  drivers/soc/fsl/dpio/qbman-portal.c | 23 +++++++++++++++++------
 | |
|  1 file changed, 17 insertions(+), 6 deletions(-)
 | |
| 
 | |
| --- a/drivers/soc/fsl/dpio/qbman-portal.c
 | |
| +++ b/drivers/soc/fsl/dpio/qbman-portal.c
 | |
| @@ -90,6 +90,14 @@ enum qbman_sdqcr_fc {
 | |
|  	qbman_sdqcr_fc_up_to_3 = 1
 | |
|  };
 | |
|  
 | |
| +#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
 | |
| +#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
 | |
| +static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
 | |
| +{
 | |
| +	dcivac(p->addr_cena + offset);
 | |
| +	prefetch(p->addr_cena + offset);
 | |
| +}
 | |
| +
 | |
|  /* Portal Access */
 | |
|  
 | |
|  static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
 | |
| @@ -190,7 +198,7 @@ struct qbman_swp *qbman_swp_init(const s
 | |
|  		memset(p->addr_cena, 0, 64 * 1024);
 | |
|  
 | |
|  	reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
 | |
| -				1, /* Writes Non-cacheable */
 | |
| +				0, /* Writes cacheable */
 | |
|  				0, /* EQCR_CI stashing threshold */
 | |
|  				3, /* RPM: Valid bit mode, RCR in array mode */
 | |
|  				2, /* DCM: Discrete consumption ack mode */
 | |
| @@ -329,6 +337,7 @@ void qbman_swp_mc_submit(struct qbman_sw
 | |
|  	if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) {
 | |
|  		dma_wmb();
 | |
|  		*v = cmd_verb | p->mc.valid_bit;
 | |
| +		dccvac(cmd);
 | |
|  	} else {
 | |
|  		*v = cmd_verb | p->mc.valid_bit;
 | |
|  		dma_wmb();
 | |
| @@ -345,6 +354,7 @@ void *qbman_swp_mc_result(struct qbman_s
 | |
|  	u32 *ret, verb;
 | |
|  
 | |
|  	if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) {
 | |
| +		qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
 | |
|  		ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
 | |
|  		/* Remove the valid-bit - command completed if the rest
 | |
|  		 * is non-zero.
 | |
| @@ -481,6 +491,7 @@ int qbman_swp_enqueue(struct qbman_swp *
 | |
|  		/* Set the verb byte, have to substitute in the valid-bit */
 | |
|  		dma_wmb();
 | |
|  		p->verb = d->verb | EQAR_VB(eqar);
 | |
| +		dccvac(p);
 | |
|  	} else {
 | |
|  		p->verb = d->verb | EQAR_VB(eqar);
 | |
|  		dma_wmb();
 | |
| @@ -677,6 +688,7 @@ int qbman_swp_pull(struct qbman_swp *s,
 | |
|  		/* Set the verb byte, have to substitute in the valid-bit */
 | |
|  		p->verb = d->verb | s->vdq.valid_bit;
 | |
|  		s->vdq.valid_bit ^= QB_VALID_BIT;
 | |
| +		dccvac(p);
 | |
|  	} else {
 | |
|  		p->verb = d->verb | s->vdq.valid_bit;
 | |
|  		s->vdq.valid_bit ^= QB_VALID_BIT;
 | |
| @@ -736,8 +748,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
 | |
|  				 s->dqrr.next_idx, pi);
 | |
|  			s->dqrr.reset_bug = 0;
 | |
|  		}
 | |
| -		prefetch(qbman_get_cmd(s,
 | |
| -				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
 | |
| +		qbman_inval_prefetch(s,	QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
 | |
|  	}
 | |
|  
 | |
|  	if ((s->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000)
 | |
| @@ -755,8 +766,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
 | |
|  	 * knew from reading PI.
 | |
|  	 */
 | |
|  	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
 | |
| -		prefetch(qbman_get_cmd(s,
 | |
| -				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
 | |
| +		qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
 | |
|  		return NULL;
 | |
|  	}
 | |
|  	/*
 | |
| @@ -779,7 +789,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
 | |
|  	    (flags & DPAA2_DQ_STAT_EXPIRED))
 | |
|  		atomic_inc(&s->vdq.available);
 | |
|  
 | |
| -	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
 | |
| +	qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
 | |
|  
 | |
|  	return p;
 | |
|  }
 | |
| @@ -911,6 +921,7 @@ int qbman_swp_release(struct qbman_swp *
 | |
|  		 */
 | |
|  		dma_wmb();
 | |
|  		p->verb = d->verb | RAR_VB(rar) | num_buffers;
 | |
| +		dccvac(p);
 | |
|  	} else {
 | |
|  		p->verb = d->verb | RAR_VB(rar) | num_buffers;
 | |
|  		dma_wmb();
 |