9a0155bc4f
Add Kernel 5.15 patches + config. This is currently only available for the generic subtarget, as it was exclusively tested with this target. Tested-on: Siemens WS-AP3610, Enterasys WS-AP3705i Signed-off-by: David Bauer <mail@david-bauer.net>
58 lines
1.9 KiB
Diff
58 lines
1.9 KiB
Diff
From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Mon, 25 Jun 2018 15:52:10 +0200
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Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
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With the driver being converted from platform_data to pure OF, we need to
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also add some docs.
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Cc: Rob Herring <robh+dt@kernel.org>
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Cc: devicetree@vger.kernel.org
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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.../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
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@@ -0,0 +1,38 @@
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+* Qualcomm Atheros AR7100 PCI express root complex
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+
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+Required properties:
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+- compatible: should contain "qcom,ar7100-pci" to identify the core.
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+- reg: Should contain the register ranges as listed in the reg-names property.
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+- reg-names: Definition: Must include the following entries
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+ - "cfg_base" IO Memory
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+- #address-cells: set to <3>
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+- #size-cells: set to <2>
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+- ranges: ranges for the PCI memory and I/O regions
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+- interrupt-map-mask and interrupt-map: standard PCI
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+ properties to define the mapping of the PCIe interface to interrupt
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+ numbers.
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+- #interrupt-cells: set to <1>
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+- interrupt-controller: define to enable the builtin IRQ cascade.
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+
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+Optional properties:
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+- interrupt-parent: phandle to the MIPS IRQ controller
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+
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+* Example for ar7100
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+ pcie-controller@180c0000 {
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+ compatible = "qca,ar7100-pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x0 0x0>;
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+ reg = <0x17010000 0x100>;
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+ reg-names = "cfg_base";
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+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
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+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <2>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-map-mask = <0 0 0 1>;
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+ interrupt-map = <0 0 0 0 &pcie0 0>;
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+ };
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