b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 7 Nov 2022 14:29:00 +0100
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Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
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resets
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Add bindings for the missing networking resets found in IPQ8074 GCC.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
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---
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include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@@ -367,6 +367,20 @@
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#define GCC_PCIE1_AHB_ARES 129
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#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
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#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
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+#define GCC_PPE_FULL_RESET 132
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+#define GCC_UNIPHY0_SOFT_RESET 133
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+#define GCC_UNIPHY0_XPCS_RESET 134
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+#define GCC_UNIPHY1_SOFT_RESET 135
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+#define GCC_UNIPHY1_XPCS_RESET 136
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+#define GCC_UNIPHY2_SOFT_RESET 137
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+#define GCC_UNIPHY2_XPCS_RESET 138
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+#define GCC_EDMA_HW_RESET 139
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+#define GCC_NSSPORT1_RESET 140
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+#define GCC_NSSPORT2_RESET 141
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+#define GCC_NSSPORT3_RESET 142
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+#define GCC_NSSPORT4_RESET 143
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+#define GCC_NSSPORT5_RESET 144
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+#define GCC_NSSPORT6_RESET 145
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#define USB0_GDSC 0
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#define USB1_GDSC 1
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