f229f4af31
Bump kernel from 4.4.50 to 4.4.52 Refresh patches Compile tested all 4.4. targets Run tested: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
69 lines
2.6 KiB
Diff
69 lines
2.6 KiB
Diff
From 1f58043afef0dca3d12dc23ac3a35d7074412939 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Tue, 2 Feb 2016 16:30:07 +0800
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Subject: [PATCH 01/13] ARM: dts: ls1021a: add PCIe dts node
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Cherry-pick upstream patch.
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LS1021a contains two PCIe controllers. The patch adds their node to
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dts file.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 44 insertions(+)
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--- a/arch/arm/boot/dts/ls1021a.dtsi
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+++ b/arch/arm/boot/dts/ls1021a.dtsi
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@@ -539,5 +539,49 @@
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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};
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+
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+ pcie@3400000 {
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+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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+ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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+ reg-names = "regs", "config";
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+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ fsl,pcie-scfg = <&scfg 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ num-lanes = <4>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ pcie@3500000 {
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+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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+ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
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+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
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+ reg-names = "regs", "config";
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+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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+ fsl,pcie-scfg = <&scfg 1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ num-lanes = <4>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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};
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};
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